liquidio: CN23XX register setup
Adds support for initializing cn23xx device registers related to mac, input/output and pf global config. Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raghu Vatsavayi
David S. Miller
parent
72c0091293
commit
3451b97cce
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@ -214,6 +214,36 @@ void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct)
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CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_CNT_INT)));
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}
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static void cn23xx_enable_error_reporting(struct octeon_device *oct)
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{
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u32 regval;
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u32 uncorrectable_err_mask, corrtable_err_status;
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pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val);
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if (regval & CN23XX_CONFIG_PCIE_DEVCTL_MASK) {
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uncorrectable_err_mask = 0;
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corrtable_err_status = 0;
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pci_read_config_dword(oct->pci_dev,
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CN23XX_CONFIG_PCIE_UNCORRECT_ERR_MASK,
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&uncorrectable_err_mask);
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pci_read_config_dword(oct->pci_dev,
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CN23XX_CONFIG_PCIE_CORRECT_ERR_STATUS,
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&corrtable_err_status);
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dev_err(&oct->pci_dev->dev, "PCI-E Fatal error detected;\n"
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"\tdev_ctl_status_reg = 0x%08x\n"
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"\tuncorrectable_error_mask_reg = 0x%08x\n"
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"\tcorrectable_error_status_reg = 0x%08x\n",
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regval, uncorrectable_err_mask,
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corrtable_err_status);
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}
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regval |= 0xf; /* Enable Link error reporting */
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dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Enabling PCI-E error reporting..\n",
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oct->octeon_id);
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pci_write_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, regval);
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}
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static u32 cn23xx_coprocessor_clock(struct octeon_device *oct)
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{
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/* Bits 29:24 of RST_BOOT[PNR_MUL] holds the ref.clock MULTIPLIER
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@ -224,6 +254,234 @@ static u32 cn23xx_coprocessor_clock(struct octeon_device *oct)
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return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50);
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}
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u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us)
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{
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/* This gives the SLI clock per microsec */
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u32 oqticks_per_us = cn23xx_coprocessor_clock(oct);
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oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us;
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/* This gives the clock cycles per millisecond */
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oqticks_per_us *= 1000;
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/* This gives the oq ticks (1024 core clock cycles) per millisecond */
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oqticks_per_us /= 1024;
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/* time_intr is in microseconds. The next 2 steps gives the oq ticks
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* corressponding to time_intr.
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*/
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oqticks_per_us *= time_intr_in_us;
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oqticks_per_us /= 1000;
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return oqticks_per_us;
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}
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static void cn23xx_setup_global_mac_regs(struct octeon_device *oct)
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{
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u64 reg_val;
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u16 mac_no = oct->pcie_port;
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u16 pf_num = oct->pf_num;
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/* programming SRN and TRS for each MAC(0..3) */
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dev_dbg(&oct->pci_dev->dev, "%s:Using pcie port %d\n",
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__func__, mac_no);
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/* By default, mapping all 64 IOQs to a single MACs */
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reg_val =
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octeon_read_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num));
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if (oct->rev_id == OCTEON_CN23XX_REV_1_1) {
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/* setting SRN <6:0> */
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reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
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} else {
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/* setting SRN <6:0> */
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reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF;
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}
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/* setting TRS <23:16> */
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reg_val = reg_val |
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(oct->sriov_info.trs << CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS);
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/* write these settings to MAC register */
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octeon_write_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num),
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reg_val);
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dev_dbg(&oct->pci_dev->dev, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n",
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mac_no, pf_num, (u64)octeon_read_csr64
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(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num)));
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}
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static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)
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{
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u32 q_no, ern, srn;
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u64 pf_num;
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u64 intr_threshold, reg_val;
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struct octeon_instr_queue *iq;
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struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
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pf_num = oct->pf_num;
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srn = oct->sriov_info.pf_srn;
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ern = srn + oct->sriov_info.num_pf_rings;
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/** Set the MAC_NUM and PVF_NUM in IQ_PKT_CONTROL reg
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* for all queues.Only PF can set these bits.
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* bits 29:30 indicate the MAC num.
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* bits 32:47 indicate the PVF num.
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*/
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for (q_no = 0; q_no < ern; q_no++) {
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reg_val = oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;
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reg_val |= pf_num << CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
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octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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reg_val);
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}
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/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
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* pf queues
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*/
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for (q_no = srn; q_no < ern; q_no++) {
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void __iomem *inst_cnt_reg;
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iq = oct->instr_queue[q_no];
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if (iq)
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inst_cnt_reg = iq->inst_cnt_reg;
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else
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inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr +
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CN23XX_SLI_IQ_INSTR_COUNT64(q_no);
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reg_val =
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octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
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reg_val |= CN23XX_PKT_INPUT_CTL_MASK;
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octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
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reg_val);
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/* Set WMARK level for triggering PI_INT */
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/* intr_threshold = CN23XX_DEF_IQ_INTR_THRESHOLD & */
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intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) &
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CN23XX_PKT_IN_DONE_WMARK_MASK;
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writeq((readq(inst_cnt_reg) &
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~(CN23XX_PKT_IN_DONE_WMARK_MASK <<
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CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) |
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(intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS),
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inst_cnt_reg);
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}
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return 0;
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}
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static void cn23xx_pf_setup_global_output_regs(struct octeon_device *oct)
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{
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u32 reg_val;
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u32 q_no, ern, srn;
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u64 time_threshold;
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struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
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srn = oct->sriov_info.pf_srn;
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ern = srn + oct->sriov_info.num_pf_rings;
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if (CFG_GET_IS_SLI_BP_ON(cn23xx->conf)) {
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octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 32);
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} else {
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/** Set Output queue watermark to 0 to disable backpressure */
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octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 0);
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}
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for (q_no = srn; q_no < ern; q_no++) {
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reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
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/* set IPTR & DPTR */
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reg_val |=
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(CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
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/* reset BMODE */
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap
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* for Output Queue ScatterList
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* reset ROR_P, NSR_P
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*/
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
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#ifdef __LITTLE_ENDIAN_BITFIELD
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
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#else
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
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#endif
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap
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* for Output Queue Data
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* reset ROR, NSR
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*/
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
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/* set the ES bit */
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
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/* write all the selected settings */
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octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val);
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/* Enabling these interrupt in oct->fn_list.enable_interrupt()
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* routine which called after IOQ init.
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* Set up interrupt packet and time thresholds
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* for all the OQs
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*/
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time_threshold = cn23xx_pf_get_oq_ticks(
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oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
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octeon_write_csr64(oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
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(CFG_GET_OQ_INTR_PKT(cn23xx->conf) |
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(time_threshold << 32)));
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}
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/** Setting the water mark level for pko back pressure **/
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writeq(0x40, (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_WMARK);
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/** Disabling setting OQs in reset when ring has no dorebells
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* enabling this will cause of head of line blocking
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*/
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/* Do it only for pass1.1. and pass1.2 */
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if ((oct->rev_id == OCTEON_CN23XX_REV_1_0) ||
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(oct->rev_id == OCTEON_CN23XX_REV_1_1))
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writeq(readq((u8 *)oct->mmio[0].hw_addr +
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CN23XX_SLI_GBL_CONTROL) | 0x2,
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(u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_GBL_CONTROL);
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/** Enable channel-level backpressure */
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if (oct->pf_num)
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writeq(0xffffffffffffffffULL,
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(u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN2_W1S);
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else
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writeq(0xffffffffffffffffULL,
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(u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN_W1S);
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}
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static int cn23xx_setup_pf_device_regs(struct octeon_device *oct)
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{
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cn23xx_enable_error_reporting(oct);
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/* program the MAC(0..3)_RINFO before setting up input/output regs */
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cn23xx_setup_global_mac_regs(oct);
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if (cn23xx_pf_setup_global_input_regs(oct))
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return -1;
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cn23xx_pf_setup_global_output_regs(oct);
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/* Default error timeout value should be 0x200000 to avoid host hang
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* when reads invalid register
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*/
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octeon_write_csr64(oct, CN23XX_SLI_WINDOW_CTL,
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CN23XX_SLI_WINDOW_CTL_DEFAULT);
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/* set SLI_PKT_IN_JABBER to handle large VXLAN packets */
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octeon_write_csr64(oct, CN23XX_SLI_PKT_IN_JABBER, CN23XX_INPUT_JABBER);
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return 0;
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}
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static void cn23xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no)
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{
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struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
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@ -433,6 +691,7 @@ int setup_cn23xx_octeon_pf_device(struct octeon_device *oct)
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oct->fn_list.setup_iq_regs = cn23xx_setup_iq_regs;
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oct->fn_list.setup_oq_regs = cn23xx_setup_oq_regs;
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oct->fn_list.setup_device_regs = cn23xx_setup_pf_device_regs;
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cn23xx_setup_reg_address(oct);
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@ -3695,6 +3695,22 @@ static int octeon_device_init(struct octeon_device *octeon_dev)
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octeon_set_io_queues_off(octeon_dev);
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if (OCTEON_CN23XX_PF(octeon_dev)) {
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ret = octeon_dev->fn_list.setup_device_regs(octeon_dev);
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if (ret) {
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dev_err(&octeon_dev->pci_dev->dev, "OCTEON: Failed to configure device registers\n");
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return ret;
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}
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}
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/* Initialize soft command buffer pool
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*/
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if (octeon_setup_sc_buffer_pool(octeon_dev)) {
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dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
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return 1;
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}
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atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
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/* Setup the data structures that manage this Octeon's Input queues. */
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if (octeon_setup_instr_queues(octeon_dev)) {
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dev_err(&octeon_dev->pci_dev->dev,
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@ -3706,14 +3722,6 @@ static int octeon_device_init(struct octeon_device *octeon_dev)
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}
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atomic_set(&octeon_dev->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
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/* Initialize soft command buffer pool
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*/
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if (octeon_setup_sc_buffer_pool(octeon_dev)) {
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dev_err(&octeon_dev->pci_dev->dev, "sc buffer pool allocation failed\n");
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return 1;
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}
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atomic_set(&octeon_dev->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
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/* Initialize lists to manage the requests of different types that
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* arrive from user & kernel applications for this octeon device.
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*/
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@ -120,6 +120,9 @@
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#define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
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#define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
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#define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
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#define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
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#define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs)
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#define CFG_GET_OQ_INFO_PTR(cfg) ((cfg)->oq.info_ptr)
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#define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr)
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@ -276,6 +276,42 @@ struct octdev_props {
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struct net_device *netdev;
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};
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struct octeon_pf_vf_hs_word {
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#ifdef __LITTLE_ENDIAN_BITFIELD
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/** PKIND value assigned for the DPI interface */
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u64 pkind : 8;
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/** OCTEON core clock multiplier */
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u64 core_tics_per_us : 16;
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/** OCTEON coprocessor clock multiplier */
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u64 coproc_tics_per_us : 16;
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/** app that currently running on OCTEON */
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u64 app_mode : 8;
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/** RESERVED */
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u64 reserved : 16;
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#else
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/** RESERVED */
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u64 reserved : 16;
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/** app that currently running on OCTEON */
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u64 app_mode : 8;
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/** OCTEON coprocessor clock multiplier */
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u64 coproc_tics_per_us : 16;
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/** OCTEON core clock multiplier */
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u64 core_tics_per_us : 16;
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/** PKIND value assigned for the DPI interface */
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u64 pkind : 8;
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#endif
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};
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struct octeon_sriov_info {
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/* Actual rings left for PF device */
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u32 num_pf_rings;
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@ -413,6 +449,8 @@ struct octeon_device {
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struct octeon_sriov_info sriov_info;
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struct octeon_pf_vf_hs_word pfvf_hsword;
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int rx_pause;
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int tx_pause;
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