ARM: S5PV310: Adds SDMMC clock for S5PV310
This patch adds SDMMC clocks for S5PV310/S5PC210. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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37e017292f
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@ -51,11 +51,21 @@ static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
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return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
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}
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static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
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}
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static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
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}
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static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
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}
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static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
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@ -336,6 +346,36 @@ static struct clk init_clocks_disable[] = {
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.parent = &clk_aclk_100.clk,
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.enable = s5pv310_clk_ip_peril_ctrl,
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.ctrlbit = (1<<24),
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}, {
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.name = "hsmmc",
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.id = 0,
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.parent = &clk_aclk_133.clk,
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.enable = s5pv310_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 5),
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}, {
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.name = "hsmmc",
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.id = 1,
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.parent = &clk_aclk_133.clk,
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.enable = s5pv310_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 6),
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}, {
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.name = "hsmmc",
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.id = 2,
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.parent = &clk_aclk_133.clk,
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.enable = s5pv310_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = "hsmmc",
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.id = 3,
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.parent = &clk_aclk_133.clk,
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.enable = s5pv310_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = "hsmmc",
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.id = 4,
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.parent = &clk_aclk_133.clk,
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.enable = s5pv310_clk_ip_fsys_ctrl,
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.ctrlbit = (1 << 9),
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}
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};
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@ -390,6 +430,56 @@ static struct clksrc_sources clkset_group = {
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.nr_sources = ARRAY_SIZE(clkset_group_list),
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};
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static struct clksrc_clk clk_dout_mmc0 = {
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.clk = {
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.name = "dout_mmc0",
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.id = -1,
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clk_dout_mmc1 = {
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.clk = {
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.name = "dout_mmc1",
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.id = -1,
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
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};
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static struct clksrc_clk clk_dout_mmc2 = {
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.clk = {
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.name = "dout_mmc2",
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.id = -1,
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clk_dout_mmc3 = {
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.clk = {
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.name = "dout_mmc3",
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.id = -1,
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
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};
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static struct clksrc_clk clk_dout_mmc4 = {
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.clk = {
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.name = "dout_mmc4",
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.id = -1,
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},
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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@ -441,7 +531,52 @@ static struct clksrc_clk clksrcs[] = {
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.sources = &clkset_group,
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.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
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},
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 0,
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.parent = &clk_dout_mmc0.clk,
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.enable = s5pv310_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 0),
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},
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.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 1,
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.parent = &clk_dout_mmc1.clk,
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.enable = s5pv310_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 4),
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},
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.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 2,
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.parent = &clk_dout_mmc2.clk,
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.enable = s5pv310_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 8),
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},
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.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 3,
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.parent = &clk_dout_mmc3.clk,
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.enable = s5pv310_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 12),
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},
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.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 4,
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.parent = &clk_dout_mmc4.clk,
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.enable = s5pv310_clksrc_mask_fsys_ctrl,
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.ctrlbit = (1 << 16),
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},
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.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
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}
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};
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/* Clock initialization code */
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@ -469,6 +604,11 @@ static struct clksrc_clk *sysclks[] = {
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&clk_aclk_100,
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&clk_aclk_160,
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&clk_aclk_133,
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&clk_dout_mmc0,
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&clk_dout_mmc1,
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&clk_dout_mmc2,
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&clk_dout_mmc3,
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&clk_dout_mmc4,
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};
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void __init_or_cpufreq s5pv310_setup_clocks(void)
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