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drm/i915/icl: program MG_DP_MODE 

Programming this register is part of the Enable Sequence for
DisplayPort on ICL. Do as the spec says.

v2: Simple rebase.

Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180725002813.6938-5-paulo.r.zanoni@intel.com
This commit is contained in:
Paulo Zanoni 2018-07-24 17:28:12 -07:00
parent db7295c2c4
commit 340a44bef2
4 changed files with 84 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/drm/i915/i915_reg.h
View File

@ -2092,6 +2092,21 @@ enum i915_power_well_id {
#define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25)
#define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24)
#define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0
#define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0
#define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0
#define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0
#define MG_DP_MODE_LN0_ACU_PORT3 0x16A3A0
#define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0
#define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0
#define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0
#define MG_DP_MODE(port, ln) \
MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \
MG_DP_MODE_LN0_ACU_PORT2, \
MG_DP_MODE_LN1_ACU_PORT1)
#define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7)
#define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6)
/* The spec defines this only for BXT PHY0, but lets assume that this
* would exist for PHY1 too if it had a second channel.
*/

2
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -2809,6 +2809,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
icl_program_mg_dp_mode(intel_dp);
if (IS_ICELAKE(dev_priv))
icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
level, encoder->type);

66
drivers/gpu/drm/i915/intel_dp.c
View File

@ -229,6 +229,72 @@ intel_dp_link_required(int pixel_clock, int bpp)
return DIV_ROUND_UP(pixel_clock * bpp, 8);
}
void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
enum port port = intel_dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
u32 ln0, ln1, lane_info;
if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
return;
ln0 = I915_READ(MG_DP_MODE(port, 0));
ln1 = I915_READ(MG_DP_MODE(port, 1));
switch (intel_dig_port->tc_type) {
case TC_PORT_TYPEC:
ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
DP_LANE_ASSIGNMENT_SHIFT(tc_port);
switch (lane_info) {
case 0x1:
case 0x4:
break;
case 0x2:
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
break;
case 0x3:
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
MG_DP_MODE_CFG_DP_X2_MODE;
break;
case 0x8:
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
break;
case 0xC:
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
MG_DP_MODE_CFG_DP_X2_MODE;
break;
case 0xF:
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
MG_DP_MODE_CFG_DP_X2_MODE;
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
MG_DP_MODE_CFG_DP_X2_MODE;
break;
default:
MISSING_CASE(lane_info);
}
break;
case TC_PORT_LEGACY:
ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
break;
default:
MISSING_CASE(intel_dig_port->tc_type);
return;
}
I915_WRITE(MG_DP_MODE(port, 0), ln0);
I915_WRITE(MG_DP_MODE(port, 1), ln1);
}
int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{

1
drivers/gpu/drm/i915/intel_drv.h
View File

@ -1714,6 +1714,7 @@ void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
unsigned int frontbuffer_bits);
void icl_program_mg_dp_mode(struct intel_dp *intel_dp);
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,