mtd: rawnand: stm32_fmc2: add polling mode
This patch adds the polling mode, a basic mode that do not need any DMA channels. This mode is also useful for debug purpose. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Christophe Kerello
Miquel Raynal
parent
2cd457f328
commit
33c8cf4215
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@ -207,6 +207,12 @@ enum stm32_fmc2_ecc {
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FMC2_ECC_BCH8 = 8
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};
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enum stm32_fmc2_irq_state {
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FMC2_IRQ_UNKNOWN = 0,
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FMC2_IRQ_BCH,
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FMC2_IRQ_SEQ
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};
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struct stm32_fmc2_timings {
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u8 tclr;
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u8 tar;
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@ -241,6 +247,7 @@ struct stm32_fmc2_nfc {
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phys_addr_t io_phys_addr;
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phys_addr_t data_phys_addr[FMC2_MAX_CE];
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struct clk *clk;
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u8 irq_state;
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struct dma_chan *dma_tx_ch;
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struct dma_chan *dma_rx_ch;
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@ -400,6 +407,17 @@ static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
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writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Enable/disable ECC */
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static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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pcr &= ~FMC2_PCR_ECCEN;
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if (enable)
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pcr |= FMC2_PCR_ECCEN;
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writel(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Enable irq sources in case of the sequencer is used */
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static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2)
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{
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@ -407,6 +425,8 @@ static inline void stm32_fmc2_enable_seq_irq(struct stm32_fmc2_nfc *fmc2)
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csqier |= FMC2_CSQIER_TCIE;
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fmc2->irq_state = FMC2_IRQ_SEQ;
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writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
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}
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@ -418,6 +438,8 @@ static inline void stm32_fmc2_disable_seq_irq(struct stm32_fmc2_nfc *fmc2)
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csqier &= ~FMC2_CSQIER_TCIE;
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writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
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fmc2->irq_state = FMC2_IRQ_UNKNOWN;
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}
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/* Clear irq sources in case of the sequencer is used */
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@ -426,6 +448,68 @@ static inline void stm32_fmc2_clear_seq_irq(struct stm32_fmc2_nfc *fmc2)
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writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, fmc2->io_base + FMC2_CSQICR);
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}
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/* Enable irq sources in case of bch is used */
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static inline void stm32_fmc2_enable_bch_irq(struct stm32_fmc2_nfc *fmc2,
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int mode)
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{
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u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
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if (mode == NAND_ECC_WRITE)
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bchier |= FMC2_BCHIER_EPBRIE;
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else
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bchier |= FMC2_BCHIER_DERIE;
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fmc2->irq_state = FMC2_IRQ_BCH;
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writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
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}
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/* Disable irq sources in case of bch is used */
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static inline void stm32_fmc2_disable_bch_irq(struct stm32_fmc2_nfc *fmc2)
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{
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u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
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bchier &= ~FMC2_BCHIER_DERIE;
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bchier &= ~FMC2_BCHIER_EPBRIE;
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writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
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fmc2->irq_state = FMC2_IRQ_UNKNOWN;
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}
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/* Clear irq sources in case of bch is used */
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static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
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{
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writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
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}
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/*
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* Enable ECC logic and reset syndrome/parity bits previously calculated
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* Syndrome/parity bits is cleared by setting the ECCEN bit to 0
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*/
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static void stm32_fmc2_hwctl(struct nand_chip *chip, int mode)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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stm32_fmc2_set_ecc(fmc2, false);
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if (chip->ecc.strength != FMC2_ECC_HAM) {
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u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
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if (mode == NAND_ECC_WRITE)
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pcr |= FMC2_PCR_WEN;
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else
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pcr &= ~FMC2_PCR_WEN;
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writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
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reinit_completion(&fmc2->complete);
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stm32_fmc2_clear_bch_irq(fmc2);
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stm32_fmc2_enable_bch_irq(fmc2, mode);
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}
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stm32_fmc2_set_ecc(fmc2, true);
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}
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/*
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* ECC Hamming calculation
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* ECC is 3 bytes for 512 bytes of data (supports error correction up to
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@ -438,6 +522,30 @@ static inline void stm32_fmc2_ham_set_ecc(const u32 ecc_sta, u8 *ecc)
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ecc[2] = ecc_sta >> 16;
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}
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static int stm32_fmc2_ham_calculate(struct nand_chip *chip, const u8 *data,
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u8 *ecc)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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u32 sr, heccr;
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int ret;
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ret = readl_relaxed_poll_timeout(fmc2->io_base + FMC2_SR,
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sr, sr & FMC2_SR_NWRF, 10, 1000);
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if (ret) {
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dev_err(fmc2->dev, "ham timeout\n");
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return ret;
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}
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heccr = readl_relaxed(fmc2->io_base + FMC2_HECCR);
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stm32_fmc2_ham_set_ecc(heccr, ecc);
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/* Disable ECC */
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stm32_fmc2_set_ecc(fmc2, false);
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return 0;
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}
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static int stm32_fmc2_ham_correct(struct nand_chip *chip, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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@ -490,6 +598,56 @@ static int stm32_fmc2_ham_correct(struct nand_chip *chip, u8 *dat,
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return 1;
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}
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/*
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* ECC BCH calculation and correction
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* ECC is 7/13 bytes for 512 bytes of data (supports error correction up to
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* max of 4-bit/8-bit)
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*/
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static int stm32_fmc2_bch_calculate(struct nand_chip *chip, const u8 *data,
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u8 *ecc)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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u32 bchpbr;
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/* Wait until the BCH code is ready */
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if (!wait_for_completion_timeout(&fmc2->complete,
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msecs_to_jiffies(1000))) {
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dev_err(fmc2->dev, "bch timeout\n");
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stm32_fmc2_disable_bch_irq(fmc2);
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return -ETIMEDOUT;
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}
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/* Read parity bits */
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bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR1);
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ecc[0] = bchpbr;
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ecc[1] = bchpbr >> 8;
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ecc[2] = bchpbr >> 16;
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ecc[3] = bchpbr >> 24;
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bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR2);
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ecc[4] = bchpbr;
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ecc[5] = bchpbr >> 8;
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ecc[6] = bchpbr >> 16;
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if (chip->ecc.strength == FMC2_ECC_BCH8) {
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ecc[7] = bchpbr >> 24;
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bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR3);
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ecc[8] = bchpbr;
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ecc[9] = bchpbr >> 8;
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ecc[10] = bchpbr >> 16;
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ecc[11] = bchpbr >> 24;
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bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR4);
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ecc[12] = bchpbr;
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}
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/* Disable ECC */
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stm32_fmc2_set_ecc(fmc2, false);
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return 0;
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}
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/* BCH algorithm correction */
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static int stm32_fmc2_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
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{
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@ -530,6 +688,94 @@ static int stm32_fmc2_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta)
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return nb_errs;
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}
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static int stm32_fmc2_bch_correct(struct nand_chip *chip, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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u32 ecc_sta[5];
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/* Wait until the decoding error is ready */
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if (!wait_for_completion_timeout(&fmc2->complete,
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msecs_to_jiffies(1000))) {
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dev_err(fmc2->dev, "bch timeout\n");
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stm32_fmc2_disable_bch_irq(fmc2);
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return -ETIMEDOUT;
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}
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ecc_sta[0] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR0);
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ecc_sta[1] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR1);
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ecc_sta[2] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR2);
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ecc_sta[3] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR3);
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ecc_sta[4] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR4);
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/* Disable ECC */
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stm32_fmc2_set_ecc(fmc2, false);
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return stm32_fmc2_bch_decode(chip->ecc.size, dat, ecc_sta);
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}
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static int stm32_fmc2_read_page(struct nand_chip *chip, u8 *buf,
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int oob_required, int page)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret, i, s, stat, eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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int eccsteps = chip->ecc.steps;
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int eccstrength = chip->ecc.strength;
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u8 *p = buf;
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u8 *ecc_calc = chip->ecc.calc_buf;
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u8 *ecc_code = chip->ecc.code_buf;
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unsigned int max_bitflips = 0;
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ret = nand_read_page_op(chip, page, 0, NULL, 0);
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if (ret)
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return ret;
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for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps;
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s++, i += eccbytes, p += eccsize) {
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chip->ecc.hwctl(chip, NAND_ECC_READ);
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/* Read the nand page sector (512 bytes) */
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ret = nand_change_read_column_op(chip, s * eccsize, p,
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eccsize, false);
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if (ret)
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return ret;
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/* Read the corresponding ECC bytes */
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ret = nand_change_read_column_op(chip, i, ecc_code,
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eccbytes, false);
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if (ret)
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return ret;
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/* Correct the data */
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stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc);
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if (stat == -EBADMSG)
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/* Check for empty pages with bitflips */
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stat = nand_check_erased_ecc_chunk(p, eccsize,
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ecc_code, eccbytes,
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NULL, 0,
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eccstrength);
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if (stat < 0) {
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mtd->ecc_stats.failed++;
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} else {
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mtd->ecc_stats.corrected += stat;
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max_bitflips = max_t(unsigned int, max_bitflips, stat);
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}
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}
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/* Read oob */
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if (oob_required) {
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ret = nand_change_read_column_op(chip, mtd->writesize,
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chip->oob_poi, mtd->oobsize,
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false);
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if (ret)
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return ret;
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}
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return max_bitflips;
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}
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/* Sequencer read/write configuration */
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static void stm32_fmc2_rw_page_init(struct nand_chip *chip, int page,
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int raw, bool write_data)
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@ -967,7 +1213,12 @@ static irqreturn_t stm32_fmc2_irq(int irq, void *dev_id)
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{
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struct stm32_fmc2_nfc *fmc2 = (struct stm32_fmc2_nfc *)dev_id;
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stm32_fmc2_disable_seq_irq(fmc2);
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if (fmc2->irq_state == FMC2_IRQ_SEQ)
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/* Sequencer is used */
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stm32_fmc2_disable_seq_irq(fmc2);
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else if (fmc2->irq_state == FMC2_IRQ_BCH)
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/* BCH is used */
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stm32_fmc2_disable_bch_irq(fmc2);
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complete(&fmc2->complete);
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@ -1356,35 +1607,27 @@ static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)
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fmc2->dma_rx_ch = dma_request_slave_channel(fmc2->dev, "rx");
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fmc2->dma_ecc_ch = dma_request_slave_channel(fmc2->dev, "ecc");
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if (fmc2->dma_ecc_ch) {
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ret = sg_alloc_table(&fmc2->dma_ecc_sg, FMC2_MAX_SG,
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GFP_KERNEL);
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if (ret)
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return ret;
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/* Allocate a buffer to store ECC status registers */
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fmc2->ecc_buf = devm_kzalloc(fmc2->dev,
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FMC2_MAX_ECC_BUF_LEN,
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GFP_KERNEL);
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if (!fmc2->ecc_buf)
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return -ENOMEM;
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} else {
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dev_err(fmc2->dev, "ECC DMA not defined in the device tree\n");
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return -ENOENT;
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if (!fmc2->dma_tx_ch || !fmc2->dma_rx_ch || !fmc2->dma_ecc_ch) {
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dev_warn(fmc2->dev, "DMAs not defined in the device tree, polling mode is used\n");
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return 0;
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}
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if (fmc2->dma_tx_ch && fmc2->dma_rx_ch) {
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ret = sg_alloc_table(&fmc2->dma_data_sg, FMC2_MAX_SG,
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GFP_KERNEL);
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if (ret)
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return ret;
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ret = sg_alloc_table(&fmc2->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL);
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if (ret)
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return ret;
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init_completion(&fmc2->dma_data_complete);
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init_completion(&fmc2->dma_ecc_complete);
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} else {
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dev_err(fmc2->dev, "rx/tx DMA not defined in the device tree\n");
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return -ENOENT;
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}
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/* Allocate a buffer to store ECC status registers */
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fmc2->ecc_buf = devm_kzalloc(fmc2->dev, FMC2_MAX_ECC_BUF_LEN,
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GFP_KERNEL);
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if (!fmc2->ecc_buf)
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return -ENOMEM;
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ret = sg_alloc_table(&fmc2->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL);
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if (ret)
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return ret;
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init_completion(&fmc2->dma_data_complete);
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init_completion(&fmc2->dma_ecc_complete);
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return 0;
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}
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@ -1392,12 +1635,34 @@ static int stm32_fmc2_dma_setup(struct stm32_fmc2_nfc *fmc2)
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/* NAND callbacks setup */
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static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
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{
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/* Specific callbacks to read/write a page */
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chip->ecc.correct = stm32_fmc2_sequencer_correct;
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chip->ecc.write_page = stm32_fmc2_sequencer_write_page;
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chip->ecc.read_page = stm32_fmc2_sequencer_read_page;
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chip->ecc.write_page_raw = stm32_fmc2_sequencer_write_page_raw;
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chip->ecc.read_page_raw = stm32_fmc2_sequencer_read_page_raw;
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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/*
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* Specific callbacks to read/write a page depending on
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* the mode (polling/sequencer) and the algo used (Hamming, BCH).
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*/
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if (fmc2->dma_tx_ch && fmc2->dma_rx_ch && fmc2->dma_ecc_ch) {
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/* DMA => use sequencer mode callbacks */
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chip->ecc.correct = stm32_fmc2_sequencer_correct;
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chip->ecc.write_page = stm32_fmc2_sequencer_write_page;
|
||||
chip->ecc.read_page = stm32_fmc2_sequencer_read_page;
|
||||
chip->ecc.write_page_raw = stm32_fmc2_sequencer_write_page_raw;
|
||||
chip->ecc.read_page_raw = stm32_fmc2_sequencer_read_page_raw;
|
||||
} else {
|
||||
/* No DMA => use polling mode callbacks */
|
||||
chip->ecc.hwctl = stm32_fmc2_hwctl;
|
||||
if (chip->ecc.strength == FMC2_ECC_HAM) {
|
||||
/* Hamming is used */
|
||||
chip->ecc.calculate = stm32_fmc2_ham_calculate;
|
||||
chip->ecc.correct = stm32_fmc2_ham_correct;
|
||||
chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK;
|
||||
} else {
|
||||
/* BCH is used */
|
||||
chip->ecc.calculate = stm32_fmc2_bch_calculate;
|
||||
chip->ecc.correct = stm32_fmc2_bch_correct;
|
||||
chip->ecc.read_page = stm32_fmc2_read_page;
|
||||
}
|
||||
}
|
||||
|
||||
/* Specific configurations depending on the algo used */
|
||||
if (chip->ecc.strength == FMC2_ECC_HAM)
|
||||
|
|
|
|||
Loading…
Reference in New Issue