mtd: rawnand: qcom: Namespace prefix some commands
PAGE_READ is used by RISC-V arch code included through mm headers, and it makes sense to bring in a prefix on these in the driver. drivers/mtd/nand/raw/qcom_nandc.c:153: warning: "PAGE_READ" redefined #define PAGE_READ 0x2 In file included from include/linux/memremap.h:7, from include/linux/mm.h:27, from include/linux/scatterlist.h:8, from include/linux/dma-mapping.h:11, from drivers/mtd/nand/raw/qcom_nandc.c:17: arch/riscv/include/asm/pgtable.h:48: note: this is the location of the previous definition Caught by riscv allmodconfig. Signed-off-by: Olof Johansson <olof@lixom.net> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
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@ -150,15 +150,15 @@
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#define NAND_VERSION_MINOR_SHIFT 16
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/* NAND OP_CMDs */
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#define PAGE_READ 0x2
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#define PAGE_READ_WITH_ECC 0x3
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#define PAGE_READ_WITH_ECC_SPARE 0x4
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#define PROGRAM_PAGE 0x6
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#define PAGE_PROGRAM_WITH_ECC 0x7
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#define PROGRAM_PAGE_SPARE 0x9
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#define BLOCK_ERASE 0xa
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#define FETCH_ID 0xb
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#define RESET_DEVICE 0xd
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#define OP_PAGE_READ 0x2
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#define OP_PAGE_READ_WITH_ECC 0x3
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#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
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#define OP_PROGRAM_PAGE 0x6
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#define OP_PAGE_PROGRAM_WITH_ECC 0x7
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#define OP_PROGRAM_PAGE_SPARE 0x9
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#define OP_BLOCK_ERASE 0xa
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#define OP_FETCH_ID 0xb
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#define OP_RESET_DEVICE 0xd
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/* Default Value for NAND_DEV_CMD_VLD */
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#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
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@ -692,11 +692,11 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
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if (read) {
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if (host->use_ecc)
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cmd = PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
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cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
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else
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cmd = PAGE_READ | PAGE_ACC | LAST_PAGE;
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cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
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} else {
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cmd = PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
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cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
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}
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if (host->use_ecc) {
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@ -1170,7 +1170,7 @@ static int nandc_param(struct qcom_nand_host *host)
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* in use. we configure the controller to perform a raw read of 512
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* bytes to read onfi params
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*/
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nandc_set_reg(nandc, NAND_FLASH_CMD, PAGE_READ | PAGE_ACC | LAST_PAGE);
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nandc_set_reg(nandc, NAND_FLASH_CMD, OP_PAGE_READ | PAGE_ACC | LAST_PAGE);
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nandc_set_reg(nandc, NAND_ADDR0, 0);
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nandc_set_reg(nandc, NAND_ADDR1, 0);
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nandc_set_reg(nandc, NAND_DEV0_CFG0, 0 << CW_PER_PAGE
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@ -1224,7 +1224,7 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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nandc_set_reg(nandc, NAND_FLASH_CMD,
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BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
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OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
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nandc_set_reg(nandc, NAND_ADDR0, page_addr);
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nandc_set_reg(nandc, NAND_ADDR1, 0);
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nandc_set_reg(nandc, NAND_DEV0_CFG0,
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@ -1255,7 +1255,7 @@ static int read_id(struct qcom_nand_host *host, int column)
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if (column == -1)
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return 0;
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nandc_set_reg(nandc, NAND_FLASH_CMD, FETCH_ID);
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nandc_set_reg(nandc, NAND_FLASH_CMD, OP_FETCH_ID);
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nandc_set_reg(nandc, NAND_ADDR0, column);
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nandc_set_reg(nandc, NAND_ADDR1, 0);
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nandc_set_reg(nandc, NAND_FLASH_CHIP_SELECT,
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@ -1276,7 +1276,7 @@ static int reset(struct qcom_nand_host *host)
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struct nand_chip *chip = &host->chip;
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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nandc_set_reg(nandc, NAND_FLASH_CMD, RESET_DEVICE);
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nandc_set_reg(nandc, NAND_FLASH_CMD, OP_RESET_DEVICE);
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nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
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write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
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