EDAC, fsl_ddr: Add support for little endian
Get endianness from device tree. Both big endian and little endian are supported. Default to big endian for backwards compatibility to MPC85xx. Signed-off-by: York Sun <york.sun@nxp.com> Acked-by: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: morbidrsa@gmail.com Cc: oss@buserror.net Cc: stuart.yoder@nxp.com Link: http://lkml.kernel.org/r/1470779760-16483-7-git-send-email-york.sun@nxp.com Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
York Sun
Borislav Petkov
parent
4e2c3252d2
commit
339fdff14c
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@ -7,6 +7,8 @@ Properties:
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"fsl,qoriq-memory-controller".
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- reg : Address and size of DDR controller registers
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- interrupts : Error interrupt of DDR controller
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- little-endian : Specifies little-endian access to registers
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If omitted, big-endian will be used.
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Example 1:
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@ -13,7 +13,6 @@
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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@ -37,6 +36,20 @@ static int edac_mc_idx;
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static u32 orig_ddr_err_disable;
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static u32 orig_ddr_err_sbe;
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static bool little_endian;
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static inline u32 ddr_in32(void __iomem *addr)
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{
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return little_endian ? ioread32(addr) : ioread32be(addr);
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}
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static inline void ddr_out32(void __iomem *addr, u32 value)
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{
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if (little_endian)
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iowrite32(value, addr);
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else
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iowrite32be(value, addr);
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}
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/************************ MC SYSFS parts ***********************************/
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@ -49,8 +62,7 @@ static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase +
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FSL_MC_DATA_ERR_INJECT_HI));
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ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
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}
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static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
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@ -60,8 +72,7 @@ static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase +
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FSL_MC_DATA_ERR_INJECT_LO));
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ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
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}
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static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
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@ -71,7 +82,7 @@ static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
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ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
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}
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static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
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@ -81,8 +92,8 @@ static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
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simple_strtoul(data, NULL, 0));
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ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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@ -95,8 +106,8 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
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simple_strtoul(data, NULL, 0));
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ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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@ -109,8 +120,8 @@ static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
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simple_strtoul(data, NULL, 0));
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ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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@ -256,7 +267,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
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int bad_data_bit;
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int bad_ecc_bit;
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err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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if (!err_detect)
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return;
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@ -265,23 +276,23 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
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/* no more processing if not ECC bit errors */
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if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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return;
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}
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syndrome = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
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syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
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/* Mask off appropriate bits of syndrome based on bus width */
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bus_width = (in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
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DSC_DBW_MASK) ? 32 : 64;
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bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
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DSC_DBW_MASK) ? 32 : 64;
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if (bus_width == 64)
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syndrome &= 0xff;
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else
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syndrome &= 0xffff;
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err_addr = make64(
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in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
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in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
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ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
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ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
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pfn = err_addr >> PAGE_SHIFT;
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for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
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@ -290,8 +301,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
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break;
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}
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cap_high = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
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cap_low = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
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cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
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cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
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/*
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* Analyze single-bit errors on 64-bit wide buses
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@ -337,7 +348,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
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row_index, 0, -1,
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mci->ctl_name, "");
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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}
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static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
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@ -346,7 +357,7 @@ static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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if (!err_detect)
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return IRQ_NONE;
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@ -366,7 +377,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
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u32 cs_bnds;
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int index;
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sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
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sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
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sdtype = sdram_ctl & DSC_SDTYPE_MASK;
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if (sdram_ctl & DSC_RD_EN) {
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@ -414,8 +425,8 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
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csrow = mci->csrows[index];
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dimm = csrow->channels[0]->dimm;
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cs_bnds = in_be32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
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(index * FSL_MC_CS_BNDS_OFS));
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cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
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(index * FSL_MC_CS_BNDS_OFS));
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start = (cs_bnds & 0xffff0000) >> 16;
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end = (cs_bnds & 0x0000ffff);
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@ -474,6 +485,12 @@ int fsl_mc_err_probe(struct platform_device *op)
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mci->ctl_name = pdata->name;
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mci->dev_name = pdata->name;
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/*
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* Get the endianness of DDR controller registers.
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* Default is big endian.
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*/
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little_endian = of_property_read_bool(op->dev.of_node, "little-endian");
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res = of_address_to_resource(op->dev.of_node, 0, &r);
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if (res) {
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pr_err("%s: Unable to get resource for MC err regs\n",
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@ -496,7 +513,7 @@ int fsl_mc_err_probe(struct platform_device *op)
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goto err;
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}
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sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
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sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
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if (!(sdram_ctl & DSC_ECC_EN)) {
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/* no ECC */
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pr_warn("%s: No ECC DIMMs discovered\n", __func__);
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@ -523,12 +540,11 @@ int fsl_mc_err_probe(struct platform_device *op)
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fsl_ddr_init_csrows(mci);
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/* store the original error disable bits */
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orig_ddr_err_disable =
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in_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
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orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
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/* clear all error bits */
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
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if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
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edac_dbg(3, "failed edac_mc_add_mc()\n");
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@ -536,15 +552,15 @@ int fsl_mc_err_probe(struct platform_device *op)
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}
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if (edac_op_state == EDAC_OPSTATE_INT) {
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out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
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DDR_EIE_MBEE | DDR_EIE_SBEE);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
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DDR_EIE_MBEE | DDR_EIE_SBEE);
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/* store the original error management threshold */
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orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
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FSL_MC_ERR_SBE) & 0xff0000;
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orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
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FSL_MC_ERR_SBE) & 0xff0000;
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/* set threshold to 1 error per interrupt */
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out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
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/* register interrupts */
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pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
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@ -586,13 +602,13 @@ int fsl_mc_err_remove(struct platform_device *op)
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edac_dbg(0, "\n");
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if (edac_op_state == EDAC_OPSTATE_INT) {
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out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
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irq_dispose_mapping(pdata->irq);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
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}
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
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orig_ddr_err_disable);
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out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
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orig_ddr_err_disable);
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ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
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edac_mc_del_mc(&op->dev);
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edac_mc_free(mci);
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