drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag

Some asic revisions need to disable PG when UVD is active.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/radeon/sumo_dpm.c

@@ -824,6 +824,8 @@ static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
 	radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
 
 	if (pi->enable_gfx_power_gating) {
+		if (!pi->disable_gfx_power_gating_in_uvd ||
+		    !r600_is_uvd_state(new_rps->class, new_rps->class2))
 			sumo_gfx_powergating_enable(rdev, true);
 	}
 }