drm/amdgpu/nv: remove some dead code
navi never supported the pci config reset. Neither did vega. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -254,31 +254,6 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
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return -EINVAL;
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}
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#if 0
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static void nv_gpu_pci_config_reset(struct amdgpu_device *adev)
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{
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u32 i;
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dev_info(adev->dev, "GPU pci config reset\n");
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/* disable BM */
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pci_clear_master(adev->pdev);
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/* reset */
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amdgpu_pci_config_reset(adev);
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udelay(100);
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/* wait for asic to come out of reset */
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for (i = 0; i < adev->usec_timeout; i++) {
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u32 memsize = nbio_v2_3_get_memsize(adev);
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if (memsize != 0xffffffff)
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break;
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udelay(1);
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}
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}
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#endif
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static int nv_asic_mode1_reset(struct amdgpu_device *adev)
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{
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u32 i;
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@ -336,15 +311,6 @@ nv_asic_reset_method(struct amdgpu_device *adev)
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static int nv_asic_reset(struct amdgpu_device *adev)
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{
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/* FIXME: it doesn't work since vega10 */
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#if 0
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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nv_gpu_pci_config_reset(adev);
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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#endif
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int ret = 0;
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struct smu_context *smu = &adev->smu;
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