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drm/nouveau/gr/gk20a: move firmware bundle release to gf100 

Some members of gf100_gr were freed by the gk20a driver. That's not
where it should be done - free them in gf100 so other chips that use
NVIDIA-provided firmware free these structures properly.

This also removes the need for a GK20A-specific destructor.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot 2016-02-24 14:42:15 +09:00 committed by Ben Skeggs
parent 5d2083d2f9
commit 336c46524f
4 changed files with 12 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -1684,6 +1684,12 @@ gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
fuc->data = NULL; fuc->data = NULL;
} }
static void
gf100_gr_dtor_init(struct gf100_gr_pack *pack)
{
vfree(pack);
}
void * void *
gf100_gr_dtor(struct nvkm_gr *base) gf100_gr_dtor(struct nvkm_gr *base)
{ {
@ -1698,6 +1704,11 @@ gf100_gr_dtor(struct nvkm_gr *base)
gf100_gr_dtor_fw(&gr->fuc41ac); gf100_gr_dtor_fw(&gr->fuc41ac);
gf100_gr_dtor_fw(&gr->fuc41ad); gf100_gr_dtor_fw(&gr->fuc41ad);
gf100_gr_dtor_init(gr->fuc_bundle);
gf100_gr_dtor_init(gr->fuc_method);
gf100_gr_dtor_init(gr->fuc_sw_ctx);
gf100_gr_dtor_init(gr->fuc_sw_nonctx);
nvkm_memory_del(&gr->unk4188b8); nvkm_memory_del(&gr->unk4188b8);
nvkm_memory_del(&gr->unk4188b4); nvkm_memory_del(&gr->unk4188b4);
return gr; return gr;

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -82,7 +82,7 @@ struct gf100_gr {
/* /*
* Used if the register packs are loaded from NVIDIA fw instead of * Used if the register packs are loaded from NVIDIA fw instead of
* using hardcoded arrays. * using hardcoded arrays. To be allocated with vzalloc().
*/ */
struct gf100_gr_pack *fuc_sw_nonctx; struct gf100_gr_pack *fuc_sw_nonctx;
struct gf100_gr_pack *fuc_sw_ctx; struct gf100_gr_pack *fuc_sw_ctx;
@ -140,7 +140,6 @@ int gk104_gr_init(struct gf100_gr *);
int gk20a_gr_new_(const struct gf100_gr_func *, struct nvkm_device *, int gk20a_gr_new_(const struct gf100_gr_func *, struct nvkm_device *,
int, struct nvkm_gr **); int, struct nvkm_gr **);
void gk20a_gr_dtor(struct gf100_gr *);
int gk20a_gr_init(struct gf100_gr *); int gk20a_gr_init(struct gf100_gr *);
int gm200_gr_init(struct gf100_gr *); int gm200_gr_init(struct gf100_gr *);

16
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View File

@ -26,12 +26,6 @@
#include <nvif/class.h> #include <nvif/class.h>
static void
gk20a_gr_init_dtor(struct gf100_gr_pack *pack)
{
vfree(pack);
}
struct gk20a_fw_av struct gk20a_fw_av
{ {
u32 addr; u32 addr;
@ -273,15 +267,6 @@ gk20a_gr_init(struct gf100_gr *gr)
return gf100_gr_init_ctxctl(gr); return gf100_gr_init_ctxctl(gr);
} }
void
gk20a_gr_dtor(struct gf100_gr *gr)
{
gk20a_gr_init_dtor(gr->fuc_method);
gk20a_gr_init_dtor(gr->fuc_bundle);
gk20a_gr_init_dtor(gr->fuc_sw_ctx);
gk20a_gr_init_dtor(gr->fuc_sw_nonctx);
}
int int
gk20a_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, gk20a_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
int index, struct nvkm_gr **pgr) int index, struct nvkm_gr **pgr)
@ -335,7 +320,6 @@ gk20a_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
static const struct gf100_gr_func static const struct gf100_gr_func
gk20a_gr = { gk20a_gr = {
.dtor = gk20a_gr_dtor,
.init = gk20a_gr_init, .init = gk20a_gr_init,
.set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask,
.ppc_nr = 1, .ppc_nr = 1,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
View File

@ -61,7 +61,6 @@ gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr)
static const struct gf100_gr_func static const struct gf100_gr_func
gm20b_gr = { gm20b_gr = {
.dtor = gk20a_gr_dtor,
.init = gk20a_gr_init, .init = gk20a_gr_init,
.init_gpc_mmu = gm20b_gr_init_gpc_mmu, .init_gpc_mmu = gm20b_gr_init_gpc_mmu,
.set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask,