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[SCSI] qla2xxx: Correct ISP24xx soft-reset handling. 

A driver must wait 100us before attempting an MMIO operation
to the RISC after a soft-reset has been initiated.  A
similar delay was needed with earlier ISPs.

Note: a PCI config-space read is used to flush the MMIO
write to the ISP, since the ISP's state machines are unable
to respond to any MMIO read during the reset process.

Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
This commit is contained in:
Andrew Vasquez 2005-11-08 14:37:48 -08:00 committed by James Bottomley
parent 8d5708f3b5
commit 335a1cc976
2 changed files with 8 additions and 7 deletions
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8
drivers/scsi/qla2xxx/qla_dbg.c
View File

@ -970,7 +970,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
int rval;
uint32_t cnt, timer;
uint32_t risc_address;
uint16_t mb[4];
uint16_t mb[4], wd;
uint32_t stat;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
@ -1514,10 +1514,10 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
WRT_REG_DWORD(&reg->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
RD_REG_DWORD(&reg->ctrl_status);
pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
udelay(5);
mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
for (cnt = 10000 ; cnt && mb[0]; cnt--) {
udelay(5);
@ -1525,7 +1525,7 @@ qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
barrier();
}
udelay(20);
/* Wait for soft-reset to complete. */
for (cnt = 0; cnt < 30000; cnt++) {
if ((RD_REG_DWORD(&reg->ctrl_status) &
CSRX_ISP_SOFT_RESET) == 0)

7
drivers/scsi/qla2xxx/qla_init.c
View File

@ -567,6 +567,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha)
unsigned long flags = 0;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
uint32_t cnt, d2;
uint16_t wd;
spin_lock_irqsave(&ha->hardware_lock, flags);
@ -581,10 +582,10 @@ qla24xx_reset_risc(scsi_qla_host_t *ha)
WRT_REG_DWORD(&reg->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
RD_REG_DWORD(&reg->ctrl_status);
pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
udelay(5);
d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
for (cnt = 10000 ; cnt && d2; cnt--) {
udelay(5);
@ -592,7 +593,7 @@ qla24xx_reset_risc(scsi_qla_host_t *ha)
barrier();
}
udelay(20);
/* Wait for soft-reset to complete. */
d2 = RD_REG_DWORD(&reg->ctrl_status);
for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
udelay(5);