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clk: sunxi-ng: div: Add macros using clk_parent_data and clk_hw 

Referencing parents with clk_hw pointers is more efficient and removes
the dependency on global clock names. clk_parent_data is needed when
some parent clocks are provided from another driver. Add macros for
declaring dividers that take advantage of these.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211119043545.4010-3-samuel@sholland.org
This commit is contained in:
Samuel Holland 2021-11-18 22:35:40 -06:00 committed by Maxime Ripard
parent c962f10f39
commit 3317cb17d5
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 78 additions and 0 deletions
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78
drivers/clk/sunxi-ng/ccu_div.h
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@ -108,6 +108,22 @@ struct ccu_div {
_shift, _width, _table, 0, \
_flags)
#define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \
_shift, _width, \
_table, _flags) \
struct ccu_div _struct = { \
.div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
_table), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT_HW(_name, \
_parent, \
&ccu_div_ops, \
_flags), \
} \
}
#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
_parents, _table, \
_reg, \
@ -166,6 +182,68 @@ struct ccu_div {
SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
_mshift, _mwidth, 0, _flags)
#define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
_gate, _flags) \
struct ccu_div _struct = { \
.enable = _gate, \
.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
_parents, \
&ccu_div_ops, \
_flags), \
}, \
}
#define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
_flags) \
SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, \
_muxshift, _muxwidth, \
0, _flags)
#define SUNXI_CCU_M_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
_mshift, _mwidth, _muxshift, _muxwidth, \
_gate, _flags) \
struct ccu_div _struct = { \
.enable = _gate, \
.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
_parents, \
&ccu_div_ops, \
_flags), \
}, \
}
#define SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
_mshift, _mwidth, _gate, \
_flags) \
struct ccu_div _struct = { \
.enable = _gate, \
.div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.common = { \
.reg = _reg, \
.hw.init = CLK_HW_INIT_HWS(_name, \
_parent, \
&ccu_div_ops, \
_flags), \
}, \
}
#define SUNXI_CCU_M_HWS(_struct, _name, _parent, _reg, _mshift, \
_mwidth, _flags) \
SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
_mshift, _mwidth, 0, _flags)
static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
{
struct ccu_common *common = hw_to_ccu_common(hw);