drm/amd/pm: Remove artificial freq level on Navi1x
Print Navi1x fine grained clocks in a consistent manner with other SOCs. Don't show aritificial DPM level when the current clock equals min or max. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1265,7 +1265,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type, char *buf)
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{
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uint16_t *curve_settings;
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int i, size = 0, ret = 0;
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int i, levels, size = 0, ret = 0;
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uint32_t cur_value = 0, value = 0, count = 0;
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uint32_t freq_values[3] = {0};
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uint32_t mark_index = 0;
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@ -1319,14 +1319,17 @@ static int navi10_print_clk_levels(struct smu_context *smu,
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freq_values[1] = cur_value;
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mark_index = cur_value == freq_values[0] ? 0 :
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cur_value == freq_values[2] ? 2 : 1;
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if (mark_index != 1)
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freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
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for (i = 0; i < 3; i++) {
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levels = 3;
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if (mark_index != 1) {
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levels = 2;
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freq_values[1] = freq_values[2];
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}
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for (i = 0; i < levels; i++) {
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size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
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i == mark_index ? "*" : "");
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}
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}
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break;
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case SMU_PCIE:
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