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clk: qcom: ipq8074: fix missing GPLL0 divider width 

GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Abhishek Sahu 2017-12-13 19:55:34 +05:30 committed by Stephen Boyd
parent df96401649
commit 32cae024f7
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/qcom/gcc-ipq8074.c
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@ -84,6 +84,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
static struct clk_alpha_pll_postdiv gpll0 = { static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000, .offset = 0x21000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll0", .name = "gpll0",
.parent_names = (const char *[]){ .parent_names = (const char *[]){