KVM: arm64: Store vcpu on the stack during __guest_enter()
KVM uses tpidr_el2 as its private vcpu register, which makes sense for non-vhe world switch as only KVM can access this register. This means vhe Linux has to use tpidr_el1, which KVM has to save/restore as part of the host context. If the SDEI handler code runs behind KVMs back, it mustn't access any per-cpu variables. To allow this on systems with vhe we need to make the host use tpidr_el2, saving KVM from save/restoring it. __guest_enter() stores the host_ctxt on the stack, do the same with the vcpu. Signed-off-by: James Morse <james.morse@arm.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -62,8 +62,8 @@ ENTRY(__guest_enter)
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// Store the host regs
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// Store the host regs
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save_callee_saved_regs x1
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save_callee_saved_regs x1
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// Store the host_ctxt for use at exit time
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// Store host_ctxt and vcpu for use at exit time
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str x1, [sp, #-16]!
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stp x1, x0, [sp, #-16]!
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add x18, x0, #VCPU_CONTEXT
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add x18, x0, #VCPU_CONTEXT
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@ -159,6 +159,10 @@ abort_guest_exit_end:
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ENDPROC(__guest_exit)
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ENDPROC(__guest_exit)
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ENTRY(__fpsimd_guest_restore)
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ENTRY(__fpsimd_guest_restore)
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// x0: esr
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// x1: vcpu
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// x2-x29,lr: vcpu regs
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// vcpu x0-x1 on the stack
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stp x2, x3, [sp, #-16]!
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stp x2, x3, [sp, #-16]!
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stp x4, lr, [sp, #-16]!
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stp x4, lr, [sp, #-16]!
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@ -173,7 +177,7 @@ alternative_else
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alternative_endif
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alternative_endif
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isb
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isb
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mrs x3, tpidr_el2
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mov x3, x1
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ldr x0, [x3, #VCPU_HOST_CONTEXT]
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ldr x0, [x3, #VCPU_HOST_CONTEXT]
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kern_hyp_va x0
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kern_hyp_va x0
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@ -104,6 +104,7 @@ el1_trap:
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/*
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/*
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* x0: ESR_EC
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* x0: ESR_EC
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*/
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*/
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ldr x1, [sp, #16 + 8] // vcpu stored by __guest_enter
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/*
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/*
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* We trap the first access to the FP/SIMD to save the host context
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* We trap the first access to the FP/SIMD to save the host context
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@ -116,19 +117,18 @@ alternative_if_not ARM64_HAS_NO_FPSIMD
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b.eq __fpsimd_guest_restore
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b.eq __fpsimd_guest_restore
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alternative_else_nop_endif
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alternative_else_nop_endif
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mrs x1, tpidr_el2
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mov x0, #ARM_EXCEPTION_TRAP
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mov x0, #ARM_EXCEPTION_TRAP
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b __guest_exit
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b __guest_exit
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el1_irq:
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el1_irq:
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stp x0, x1, [sp, #-16]!
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stp x0, x1, [sp, #-16]!
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mrs x1, tpidr_el2
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ldr x1, [sp, #16 + 8]
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mov x0, #ARM_EXCEPTION_IRQ
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mov x0, #ARM_EXCEPTION_IRQ
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b __guest_exit
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b __guest_exit
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el1_error:
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el1_error:
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stp x0, x1, [sp, #-16]!
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stp x0, x1, [sp, #-16]!
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mrs x1, tpidr_el2
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ldr x1, [sp, #16 + 8]
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mov x0, #ARM_EXCEPTION_EL1_SERROR
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mov x0, #ARM_EXCEPTION_EL1_SERROR
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b __guest_exit
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b __guest_exit
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