clk: renesas: r9a07g044: Add M4 Clock support
Add support for M4 clock which is sourced from pll2_533_div2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -57,6 +57,9 @@ enum clk_ids {
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CLK_SEL_GPU2,
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CLK_SEL_GPU2,
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CLK_SEL_PLL5_4,
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CLK_SEL_PLL5_4,
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CLK_DSI_DIV,
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CLK_DSI_DIV,
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CLK_PLL2_533,
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CLK_PLL2_533_DIV2,
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CLK_DIV_DSI_LPCLK,
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/* Module Clocks */
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/* Module Clocks */
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MOD_CLK_BASE,
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MOD_CLK_BASE,
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@ -80,6 +83,14 @@ static const struct clk_div_table dtable_1_32[] = {
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{0, 0},
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{0, 0},
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};
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};
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static const struct clk_div_table dtable_16_128[] = {
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{0, 16},
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{1, 32},
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{2, 64},
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{3, 128},
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{0, 0},
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};
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/* Mux clock tables */
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/* Mux clock tables */
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static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
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static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
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static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
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static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
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@ -88,7 +99,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
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static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
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static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
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static const struct {
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static const struct {
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struct cpg_core_clk common[52];
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struct cpg_core_clk common[56];
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#ifdef CONFIG_CLK_R9A07G054
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#ifdef CONFIG_CLK_R9A07G054
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struct cpg_core_clk drp[0];
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struct cpg_core_clk drp[0];
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#endif
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#endif
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@ -102,6 +113,7 @@ static const struct {
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
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DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
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DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
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DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
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@ -120,6 +132,8 @@ static const struct {
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DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
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DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
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DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
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DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
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DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
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DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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@ -137,6 +151,8 @@ static const struct {
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DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
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DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
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DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4,
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DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4,
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sel_pll5_4, ARRAY_SIZE(sel_pll5_4)),
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sel_pll5_4, ARRAY_SIZE(sel_pll5_4)),
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DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
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DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK),
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/* Core output clk */
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/* Core output clk */
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DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
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DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
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@ -169,6 +185,7 @@ static const struct {
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DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
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DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
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DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
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DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
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DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
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DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
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DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1),
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},
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},
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#ifdef CONFIG_CLK_R9A07G054
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#ifdef CONFIG_CLK_R9A07G054
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.drp = {
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.drp = {
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