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drm/amd/powerplay: enable GPO 

GPO is graphics power optimizer.
SMU calculates the 16 gfxclk V/F points according to the CU numbers
and memory activity.RLC picks one of them according to the memory
speed requirements for the data transmission.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kenneth Feng 2020-03-27 14:17:41 +08:00 committed by Alex Deucher
parent 846938c223
commit 31cb0dd9a2
2 changed files with 2 additions and 0 deletions
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1
drivers/gpu/drm/amd/powerplay/inc/smu_types.h
View File

@ -260,6 +260,7 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(MMHUB_PG), \
__SMU_DUMMY_MAP(ATHUB_PG), \
__SMU_DUMMY_MAP(APCC_DFLL), \
__SMU_DUMMY_MAP(DPM_GFX_GPO), \
__SMU_DUMMY_MAP(WAFL_CG),
#undef __SMU_DUMMY_MAP

1
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
View File

@ -126,6 +126,7 @@ static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] =
static struct smu_11_0_cmn2aisc_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
FEA_MAP(DPM_PREFETCHER),
FEA_MAP(DPM_GFXCLK),
FEA_MAP(DPM_GFX_GPO),
FEA_MAP(DPM_UCLK),
FEA_MAP(DPM_SOCCLK),
FEA_MAP(DPM_MP0CLK),