kvm: x86: mmu: Set SPTE_SPECIAL_MASK within mmu.c
Instead of the caller including the SPTE_SPECIAL_MASK in the masks being supplied to kvm_mmu_set_mmio_spte_mask() and kvm_mmu_set_mask_ptes(), those functions now themselves include the SPTE_SPECIAL_MASK. Note that bit 63 is now reset in the default MMIO mask. Signed-off-by: Junaid Shahid <junaids@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -208,7 +208,7 @@ static void mmu_free_roots(struct kvm_vcpu *vcpu);
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void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
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{
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shadow_mmio_mask = mmio_mask;
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shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK;
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}
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EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
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@ -318,6 +318,9 @@ void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
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u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask,
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u64 acc_track_mask)
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{
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if (acc_track_mask != 0)
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acc_track_mask |= SPTE_SPECIAL_MASK;
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shadow_user_mask = user_mask;
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shadow_accessed_mask = accessed_mask;
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shadow_dirty_mask = dirty_mask;
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@ -5236,10 +5236,8 @@ static void ept_set_mmio_spte_mask(void)
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/*
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* EPT Misconfigurations can be generated if the value of bits 2:0
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* of an EPT paging-structure entry is 110b (write/execute).
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* Also, special bit (62) is set to quickly identify mmio spte.
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*/
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kvm_mmu_set_mmio_spte_mask(SPTE_SPECIAL_MASK |
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VMX_EPT_MISCONFIG_WX_VALUE);
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kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE);
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}
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#define VMX_XSS_EXIT_BITMAP 0
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@ -6585,7 +6583,7 @@ void vmx_enable_tdp(void)
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enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
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0ull, VMX_EPT_EXECUTABLE_MASK,
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cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
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enable_ept_ad_bits ? 0ull : SPTE_SPECIAL_MASK | VMX_EPT_RWX_MASK);
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enable_ept_ad_bits ? 0ull : VMX_EPT_RWX_MASK);
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ept_set_mmio_spte_mask();
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kvm_enable_tdp();
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@ -5952,9 +5952,6 @@ static void kvm_set_mmio_spte_mask(void)
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/* Mask the reserved physical address bits. */
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mask = rsvd_bits(maxphyaddr, 51);
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/* Bit 62 is always reserved for 32bit host. */
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mask |= 0x3ull << 62;
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/* Set the present bit. */
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mask |= 1ull;
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