i2c: riic: add driver
Tested with a r7s72100 genmai board acessing an eeprom. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Wolfram Sang
Wolfram Sang
parent
802eee95bd
commit
310c18a414
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@ -0,0 +1,29 @@
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Device tree configuration for Renesas RIIC driver
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Required properties:
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- compatible : "renesas,riic-<soctype>". "renesas,riic-rz" as fallback
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- reg : address start and address range size of device
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- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI)
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- clock-frequency : frequency of bus clock in Hz
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- #address-cells : should be <1>
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- #size-cells : should be <0>
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Pinctrl properties might be needed, too. See there.
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Example:
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i2c0: i2c@fcfee000 {
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compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
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reg = <0xfcfee000 0x44>;
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interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
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<0 158 IRQ_TYPE_EDGE_RISING>,
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<0 159 IRQ_TYPE_EDGE_RISING>,
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<0 160 IRQ_TYPE_LEVEL_HIGH>,
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<0 161 IRQ_TYPE_LEVEL_HIGH>,
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<0 162 IRQ_TYPE_LEVEL_HIGH>,
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<0 163 IRQ_TYPE_LEVEL_HIGH>,
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<0 164 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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@ -648,6 +648,16 @@ config I2C_PXA_SLAVE
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is necessary for systems where the PXA may be a target on the
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I2C bus.
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config I2C_RIIC
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tristate "Renesas RIIC adapter"
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depends on ARCH_SHMOBILE || COMPILE_TEST
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help
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If you say yes to this option, support will be included for the
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Renesas RIIC I2C interface.
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This driver can also be built as a module. If so, the module
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will be called i2c-riic.
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config HAVE_S3C2410_I2C
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bool
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help
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@ -63,6 +63,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
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obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
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obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
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obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
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obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
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obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
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obj-$(CONFIG_I2C_S6000) += i2c-s6000.o
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obj-$(CONFIG_I2C_SH7760) += i2c-sh7760.o
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@ -0,0 +1,427 @@
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/*
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* Renesas RIIC driver
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*
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* Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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/*
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* This i2c core has a lot of interrupts, namely 8. We use their chaining as
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* some kind of state machine.
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*
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* 1) The main xfer routine kicks off a transmission by putting the start bit
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* (or repeated start) on the bus and enabling the transmit interrupt (TIE)
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* since we need to send the slave address + RW bit in every case.
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*
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* 2) TIE sends slave address + RW bit and selects how to continue.
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*
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* 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
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* are done, we switch over to the transmission done interrupt (TEIE) and mark
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* the message as completed (includes sending STOP) there.
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*
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* 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
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* needed to start clocking, then we keep receiving until we are done. Note
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* that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
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* writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
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* message to create the final NACK as sketched in the datasheet. This caused
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* some subtle races (when byte n was processed and byte n+1 was already
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* waiting), though, and I started with the safe approach.
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*
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* 4) If we got a NACK somewhere, we flag the error and stop the transmission
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* via NAKIE.
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*
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* Also check the comments in the interrupt routines for some gory details.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#define RIIC_ICCR1 0x00
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#define RIIC_ICCR2 0x04
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#define RIIC_ICMR1 0x08
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#define RIIC_ICMR3 0x10
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#define RIIC_ICSER 0x18
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#define RIIC_ICIER 0x1c
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#define RIIC_ICSR2 0x24
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#define RIIC_ICBRL 0x34
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#define RIIC_ICBRH 0x38
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#define RIIC_ICDRT 0x3c
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#define RIIC_ICDRR 0x40
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#define ICCR1_ICE 0x80
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#define ICCR1_IICRST 0x40
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#define ICCR1_SOWP 0x10
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#define ICCR2_BBSY 0x80
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#define ICCR2_SP 0x08
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#define ICCR2_RS 0x04
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#define ICCR2_ST 0x02
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#define ICMR1_CKS_MASK 0x70
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#define ICMR1_BCWP 0x08
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#define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
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#define ICMR3_RDRFS 0x20
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#define ICMR3_ACKWP 0x10
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#define ICMR3_ACKBT 0x08
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#define ICIER_TIE 0x80
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#define ICIER_TEIE 0x40
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#define ICIER_RIE 0x20
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#define ICIER_NAKIE 0x10
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#define ICSR2_NACKF 0x10
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/* ICBRx (@ PCLK 33MHz) */
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#define ICBR_RESERVED 0xe0 /* Should be 1 on writes */
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#define ICBRL_SP100K (19 | ICBR_RESERVED)
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#define ICBRH_SP100K (16 | ICBR_RESERVED)
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#define ICBRL_SP400K (21 | ICBR_RESERVED)
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#define ICBRH_SP400K (9 | ICBR_RESERVED)
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#define RIIC_INIT_MSG -1
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struct riic_dev {
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void __iomem *base;
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u8 *buf;
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struct i2c_msg *msg;
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int bytes_left;
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int err;
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int is_last;
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struct completion msg_done;
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struct i2c_adapter adapter;
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struct clk *clk;
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};
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struct riic_irq_desc {
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int res_num;
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irq_handler_t isr;
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char *name;
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};
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static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
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{
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writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
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}
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static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
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{
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struct riic_dev *riic = i2c_get_adapdata(adap);
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unsigned long time_left;
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int i, ret;
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u8 start_bit;
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ret = clk_prepare_enable(riic->clk);
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if (ret)
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return ret;
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if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
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riic->err = -EBUSY;
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goto out;
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}
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reinit_completion(&riic->msg_done);
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riic->err = 0;
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writeb(0, riic->base + RIIC_ICSR2);
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for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
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riic->bytes_left = RIIC_INIT_MSG;
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riic->buf = msgs[i].buf;
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riic->msg = &msgs[i];
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riic->is_last = (i == num - 1);
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writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
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writeb(start_bit, riic->base + RIIC_ICCR2);
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time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
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if (time_left == 0)
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riic->err = -ETIMEDOUT;
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if (riic->err)
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break;
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start_bit = ICCR2_RS;
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}
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out:
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clk_disable_unprepare(riic->clk);
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return riic->err ?: num;
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}
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static irqreturn_t riic_tdre_isr(int irq, void *data)
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{
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struct riic_dev *riic = data;
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u8 val;
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if (!riic->bytes_left)
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return IRQ_NONE;
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if (riic->bytes_left == RIIC_INIT_MSG) {
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val = !!(riic->msg->flags & I2C_M_RD);
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if (val)
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/* On read, switch over to receive interrupt */
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riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
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else
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/* On write, initialize length */
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riic->bytes_left = riic->msg->len;
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val |= (riic->msg->addr << 1);
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} else {
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val = *riic->buf;
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riic->buf++;
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riic->bytes_left--;
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}
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/*
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* Switch to transmission ended interrupt when done. Do check here
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* after bytes_left was initialized to support SMBUS_QUICK (new msg has
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* 0 length then)
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*/
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if (riic->bytes_left == 0)
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riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
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/*
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* This acks the TIE interrupt. We get another TIE immediately if our
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* value could be moved to the shadow shift register right away. So
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* this must be after updates to ICIER (where we want to disable TIE)!
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*/
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writeb(val, riic->base + RIIC_ICDRT);
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return IRQ_HANDLED;
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}
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static irqreturn_t riic_tend_isr(int irq, void *data)
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{
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struct riic_dev *riic = data;
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if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
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/* We got a NACKIE */
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readb(riic->base + RIIC_ICDRR); /* dummy read */
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riic->err = -ENXIO;
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} else if (riic->bytes_left) {
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return IRQ_NONE;
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}
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if (riic->is_last || riic->err)
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writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
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writeb(0, riic->base + RIIC_ICIER);
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complete(&riic->msg_done);
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return IRQ_HANDLED;
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}
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static irqreturn_t riic_rdrf_isr(int irq, void *data)
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{
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struct riic_dev *riic = data;
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if (!riic->bytes_left)
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return IRQ_NONE;
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if (riic->bytes_left == RIIC_INIT_MSG) {
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riic->bytes_left = riic->msg->len;
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readb(riic->base + RIIC_ICDRR); /* dummy read */
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return IRQ_HANDLED;
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}
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if (riic->bytes_left == 1) {
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/* STOP must come before we set ACKBT! */
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if (riic->is_last)
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writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
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riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
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writeb(0, riic->base + RIIC_ICIER);
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complete(&riic->msg_done);
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} else {
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riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
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}
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/* Reading acks the RIE interrupt */
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*riic->buf = readb(riic->base + RIIC_ICDRR);
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riic->buf++;
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riic->bytes_left--;
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return IRQ_HANDLED;
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}
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static u32 riic_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm riic_algo = {
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.master_xfer = riic_xfer,
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.functionality = riic_func,
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};
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static int riic_init_hw(struct riic_dev *riic, u32 spd)
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{
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int ret;
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unsigned long rate;
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ret = clk_prepare_enable(riic->clk);
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if (ret)
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return ret;
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/*
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* TODO: Implement formula to calculate the timing values depending on
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* variable parent clock rate and arbitrary bus speed
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*/
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rate = clk_get_rate(riic->clk);
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if (rate != 33325000) {
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dev_err(&riic->adapter.dev,
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"invalid parent clk (%lu). Must be 33325000Hz\n", rate);
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clk_disable_unprepare(riic->clk);
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return -EINVAL;
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}
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/* Changing the order of accessing IICRST and ICE may break things! */
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writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
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riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
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switch (spd) {
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case 100000:
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writeb(ICMR1_CKS(3), riic->base + RIIC_ICMR1);
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writeb(ICBRH_SP100K, riic->base + RIIC_ICBRH);
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writeb(ICBRL_SP100K, riic->base + RIIC_ICBRL);
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break;
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case 400000:
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writeb(ICMR1_CKS(1), riic->base + RIIC_ICMR1);
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writeb(ICBRH_SP400K, riic->base + RIIC_ICBRH);
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writeb(ICBRL_SP400K, riic->base + RIIC_ICBRL);
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break;
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default:
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dev_err(&riic->adapter.dev,
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"unsupported bus speed (%dHz). Use 100000 or 400000\n", spd);
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clk_disable_unprepare(riic->clk);
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return -EINVAL;
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}
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writeb(0, riic->base + RIIC_ICSER);
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writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
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riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
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clk_disable_unprepare(riic->clk);
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return 0;
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}
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static struct riic_irq_desc riic_irqs[] = {
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{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
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{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
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{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
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{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
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};
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static int riic_i2c_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct riic_dev *riic;
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struct i2c_adapter *adap;
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struct resource *res;
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u32 bus_rate = 0;
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int i, ret;
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riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
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if (!riic)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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riic->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(riic->base))
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return PTR_ERR(riic->base);
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riic->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(riic->clk)) {
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dev_err(&pdev->dev, "missing controller clock");
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return PTR_ERR(riic->clk);
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}
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for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
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res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num);
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if (!res)
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return -ENODEV;
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ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr,
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0, riic_irqs[i].name, riic);
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if (ret) {
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dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
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return ret;
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}
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}
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adap = &riic->adapter;
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i2c_set_adapdata(adap, riic);
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strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
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adap->owner = THIS_MODULE;
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adap->algo = &riic_algo;
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adap->dev.parent = &pdev->dev;
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adap->dev.of_node = pdev->dev.of_node;
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init_completion(&riic->msg_done);
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of_property_read_u32(np, "clock-frequency", &bus_rate);
|
||||
ret = riic_init_hw(riic, bus_rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
ret = i2c_add_adapter(adap);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to add adapter\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, riic);
|
||||
|
||||
dev_info(&pdev->dev, "registered with %dHz bus speed\n", bus_rate);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int riic_i2c_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct riic_dev *riic = platform_get_drvdata(pdev);
|
||||
|
||||
writeb(0, riic->base + RIIC_ICIER);
|
||||
i2c_del_adapter(&riic->adapter);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id riic_i2c_dt_ids[] = {
|
||||
{ .compatible = "renesas,riic-rz" },
|
||||
{ /* Sentinel */ },
|
||||
};
|
||||
|
||||
static struct platform_driver riic_i2c_driver = {
|
||||
.probe = riic_i2c_probe,
|
||||
.remove = riic_i2c_remove,
|
||||
.driver = {
|
||||
.name = "i2c-riic",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = riic_i2c_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(riic_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas RIIC adapter");
|
||||
MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
|
||||
Loading…
Reference in New Issue