drm/amd/display: Skip DPP DTO update if root clock is gated
[Why] Hardware implements root clock gating by utilizing the DPP DTO registers with a special case of DTO enabled, phase = 0, modulo = 1. This conflicts with our policy to always update the DPPDTO for cases where it's expected to be disabled. The pipes unexpectedly enter a higher power state than expected because of this programming flow. [How] Guard the upper layers of HWSS against this hardware quirk with programming the register with an internal state flag in DCCG. While technically acting as global state for the DCCG, HWSS shouldn't be expected to understand the hardware quirk for having DTO disabled causing more power than DTO enabled with this specific setting. This also prevents sequencing errors from occuring in the future if we have to program DPP DTO in multiple locations. Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -47,6 +47,14 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
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{
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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if (dccg->dpp_clock_gated[dpp_inst]) {
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/*
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* Do not update the DPPCLK DTO if the clock is stopped.
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* It is treated the same as if the pipe itself were in PG.
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*/
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return;
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}
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if (dccg->ref_dppclk && req_dppclk) {
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if (dccg->ref_dppclk && req_dppclk) {
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int ref_dppclk = dccg->ref_dppclk;
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int ref_dppclk = dccg->ref_dppclk;
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int modulo, phase;
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int modulo, phase;
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@ -332,6 +332,9 @@ static void dccg314_dpp_root_clock_control(
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{
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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if (dccg->dpp_clock_gated[dpp_inst] == clock_on)
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return;
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if (clock_on) {
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if (clock_on) {
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/* turn off the DTO and leave phase/modulo at max */
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/* turn off the DTO and leave phase/modulo at max */
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REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
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REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
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@ -345,6 +348,8 @@ static void dccg314_dpp_root_clock_control(
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DPPCLK0_DTO_PHASE, 0,
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DPPCLK0_DTO_PHASE, 0,
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DPPCLK0_DTO_MODULO, 1);
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DPPCLK0_DTO_MODULO, 1);
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}
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}
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dccg->dpp_clock_gated[dpp_inst] = !clock_on;
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}
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}
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static const struct dccg_funcs dccg314_funcs = {
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static const struct dccg_funcs dccg314_funcs = {
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@ -68,6 +68,7 @@ struct dccg {
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const struct dccg_funcs *funcs;
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const struct dccg_funcs *funcs;
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int pipe_dppclk_khz[MAX_PIPES];
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int pipe_dppclk_khz[MAX_PIPES];
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int ref_dppclk;
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int ref_dppclk;
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bool dpp_clock_gated[MAX_PIPES];
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//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
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//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
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//int audio_dtbclk_khz;/* TODO needs to be removed */
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//int audio_dtbclk_khz;/* TODO needs to be removed */
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//int ref_dtbclk_khz;/* TODO needs to be removed */
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//int ref_dtbclk_khz;/* TODO needs to be removed */
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