UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

blackfin updates for Linux 3.14 

-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJS6KruAAoJEJommM3PjknH4gEQALWipIhpo86sxKU1duay4MwW
 sP+hSvct+6O7/P/TDDcjTVkNzGZ+F7xwOqA/HmxzZTdxifyaanNzN75JLj54ci2b
 OY/Ocs259jPB74nhPoll/+XfNs9yRKFF36Clm14mlIzu/fx3yj12epzY0NHiiZhK
 KR0BSrjoXAxKsSdXqg/2QpcFIIWi0ufNPSvfVem0/03ajArcfL6HbzJPonlOSTNo
 UIzHjL29PvGZeDLo6aDgg5Ea5MY2QVnXdvq4J5ShVmbclmWZ8tXQVMShFF8nsHvZ
 XxqN5Ohp30yvscIq+FEZ164xsnRSK5x/oNB06ggCYmyMc9bCfh3ZxMYZ56l0p4xQ
 /Rq3Y4YC2lVbdc/x56Xq2Jwr+mtl1ivGClyqVSC4+OIahkNz6N7CBqzW939aGDcm
 E2lOHByYqzDLVjxpdfwhBSTzAmWtXwmNOdgaIcE41KLQV8TgEnfmW7m0ULo2itxg
 xtHk3Hji6u7G3ykc6Yrwu8RlDJGB+QumgoNuaAk/XUnVvxse1LJ0kcy2FwbZgEjy
 h9P8/iomMQjyBZLXo1zHzKtAngYIWUa15vbFKuRy9FbsRWC94d+9FB+BiPG7Ztba
 6Ub1GQJvC4XYHH6HGw7fh0zBazn4OZI8m40RtpO76s9pVf5+zKPucVWdpH6fDwjD
 TeYvpmfJOuSVJfsVzjoF
 =gvaS
 -----END PGP SIGNATURE-----

Merge tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux

Pull blackfin updates from Steven Miao:
 "Some minor changes and bug fixes"

* tag 'blackfin-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/realmz6/blackfin-linux:
  From: Eunbong Song <eunb.song@samsung.com>
  Add platfrom device resource for bfin-sport on bf533 stamp
  fix build error for bf527-ezkit_defconfig for old silicon
  blackfin: Support L1 SRAM parity checking feature on bf60x
  blackfin: bf609: update the anomaly list to Nov 2013
  blackfin: delete non-required instances of <linux/init.h>
  From: Paul Walmsley <pwalmsley@nvidia.com>
  06/18] smp, blackfin: kill SMP single function call interrupt
  arch: blackfin: uapi: be sure of "_UAPI" prefix for all guard macros
This commit is contained in:
Linus Torvalds 2014-01-29 18:24:20 -08:00
parent cac9283ca3 58095fdaaf
commit 30c867eebf
34 changed files with 166 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/blackfin/configs/BF527-EZKIT_defconfig
View File

@ -146,6 +146,7 @@ CONFIG_USB_DEVICEFS=y
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_MUSB_PIO_ONLY=y
CONFIG_USB_MUSB_BLACKFIN=y
CONFIG_MUSB_PIO_ONLY=y
CONFIG_USB_STORAGE=y

1
arch/blackfin/configs/BF538-EZKIT_defconfig
View File

@ -59,7 +59,6 @@ CONFIG_BFIN_SIR=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLOCK=y

1
arch/blackfin/configs/BF561-ACVILON_defconfig
View File

@ -49,7 +49,6 @@ CONFIG_SYN_COOKIES=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y

1
arch/blackfin/configs/BlackStamp_defconfig
View File

@ -44,7 +44,6 @@ CONFIG_IP_PNP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLOCK=y

1
arch/blackfin/configs/CM-BF533_defconfig
View File

@ -36,7 +36,6 @@ CONFIG_UNIX=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y

1
arch/blackfin/configs/CM-BF548_defconfig
View File

@ -53,7 +53,6 @@ CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y

1
arch/blackfin/configs/CM-BF561_defconfig
View File

@ -51,7 +51,6 @@ CONFIG_INET=y
# CONFIG_WIRELESS is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y

1
arch/blackfin/configs/DNP5370_defconfig
View File

@ -36,7 +36,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_DEBUG_VERBOSE=1
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_NFTL=y

1
arch/blackfin/configs/H8606_defconfig
View File

@ -36,7 +36,6 @@ CONFIG_IRTTY_SIR=m
# CONFIG_WIRELESS is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAM=y

1
arch/blackfin/configs/IP0X_defconfig
View File

@ -43,7 +43,6 @@ CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_MANGLE=y
# CONFIG_WIRELESS is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y

1
arch/blackfin/configs/PNAV-10_defconfig
View File

@ -46,7 +46,6 @@ CONFIG_IP_PNP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_RAM=y

1
arch/blackfin/configs/SRV1_defconfig
View File

@ -38,7 +38,6 @@ CONFIG_IRTTY_SIR=m
# CONFIG_WIRELESS is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=m
CONFIG_MTD_BLOCK=y
CONFIG_MTD_JEDECPROBE=m

1
arch/blackfin/configs/TCM-BF518_defconfig
View File

@ -54,7 +54,6 @@ CONFIG_IP_PNP=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y

1
arch/blackfin/include/asm/def_LPBlackfin.h
View File

@ -544,6 +544,7 @@ do { \
#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
#define RDCHK 0x9 /* Enable L1 Parity Check */
/* Masks */
#define ENDM 0x00000001 /* (doesn't really exist) Enable

5
arch/blackfin/include/uapi/asm/byteorder.h
View File

@ -1 +1,6 @@
#ifndef _UAPI__BFIN_ASM_BYTEORDER_H
#define _UAPI__BFIN_ASM_BYTEORDER_H
#include <linux/byteorder/little_endian.h>
#endif /* _UAPI__BFIN_ASM_BYTEORDER_H */

6
arch/blackfin/include/uapi/asm/cachectl.h
View File

@ -7,8 +7,8 @@
* Licensed under the GPL-2 or later.
*/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
#ifndef _UAPI_ASM_CACHECTL
#define _UAPI_ASM_CACHECTL
/*
* Options for cacheflush system call
@ -17,4 +17,4 @@
#define DCACHE (1<<1) /* writeback and flush data cache */
#define BCACHE (ICACHE|DCACHE) /* flush both caches */
#endif /* _ASM_CACHECTL */
#endif /* _UAPI_ASM_CACHECTL */

6
arch/blackfin/include/uapi/asm/fcntl.h
View File

@ -4,8 +4,8 @@
* Licensed under the GPL-2 or later.
*/
#ifndef _BFIN_FCNTL_H
#define _BFIN_FCNTL_H
#ifndef _UAPI_BFIN_FCNTL_H
#define _UAPI_BFIN_FCNTL_H
#define O_DIRECTORY 040000 /* must be a directory */
#define O_NOFOLLOW 0100000 /* don't follow links */
@ -14,4 +14,4 @@
#include <asm-generic/fcntl.h>
#endif
#endif /* _UAPI_BFIN_FCNTL_H */

6
arch/blackfin/include/uapi/asm/ioctls.h
View File

@ -1,7 +1,7 @@
#ifndef __ARCH_BFIN_IOCTLS_H__
#define __ARCH_BFIN_IOCTLS_H__
#ifndef _UAPI__ARCH_BFIN_IOCTLS_H__
#define _UAPI__ARCH_BFIN_IOCTLS_H__
#define FIOQSIZE 0x545E
#include <asm-generic/ioctls.h>
#endif
#endif /* _UAPI__ARCH_BFIN_IOCTLS_H__ */

6
arch/blackfin/include/uapi/asm/poll.h
View File

@ -5,12 +5,12 @@
*
*/
#ifndef __BFIN_POLL_H
#define __BFIN_POLL_H
#ifndef _UAPI__BFIN_POLL_H
#define _UAPI__BFIN_POLL_H
#define POLLWRNORM 4 /* POLLOUT */
#define POLLWRBAND 256
#include <asm-generic/poll.h>
#endif
#endif /* _UAPI__BFIN_POLL_H */

6
arch/blackfin/include/uapi/asm/posix_types.h
View File

@ -4,8 +4,8 @@
* Licensed under the GPL-2 or later.
*/
#ifndef __ARCH_BFIN_POSIX_TYPES_H
#define __ARCH_BFIN_POSIX_TYPES_H
#ifndef _UAPI__ARCH_BFIN_POSIX_TYPES_H
#define _UAPI__ARCH_BFIN_POSIX_TYPES_H
typedef unsigned short __kernel_mode_t;
#define __kernel_mode_t __kernel_mode_t
@ -27,4 +27,4 @@ typedef unsigned short __kernel_old_dev_t;
#include <asm-generic/posix_types.h>
#endif
#endif /* _UAPI__ARCH_BFIN_POSIX_TYPES_H */

6
arch/blackfin/include/uapi/asm/sigcontext.h
View File

@ -4,8 +4,8 @@
* Licensed under the GPL-2 or later.
*/
#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
#define _ASM_BLACKFIN_SIGCONTEXT_H
#ifndef _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
#define _UAPI_ASM_BLACKFIN_SIGCONTEXT_H
/* Add new entries at the end of the structure only. */
struct sigcontext {
@ -58,4 +58,4 @@ struct sigcontext {
unsigned long sc_seqstat;
};
#endif
#endif /* _UAPI_ASM_BLACKFIN_SIGCONTEXT_H */

6
arch/blackfin/include/uapi/asm/siginfo.h
View File

@ -4,8 +4,8 @@
* Licensed under the GPL-2 or later.
*/
#ifndef _BFIN_SIGINFO_H
#define _BFIN_SIGINFO_H
#ifndef _UAPI_BFIN_SIGINFO_H
#define _UAPI_BFIN_SIGINFO_H
#include <linux/types.h>
#include <asm-generic/siginfo.h>
@ -38,4 +38,4 @@
*/
#define SEGV_STACKFLOW (__SI_FAULT|3) /* stack overflow */
#endif
#endif /* _UAPI_BFIN_SIGINFO_H */

6
arch/blackfin/include/uapi/asm/signal.h
View File

@ -1,7 +1,7 @@
#ifndef _BLACKFIN_SIGNAL_H
#define _BLACKFIN_SIGNAL_H
#ifndef _UAPI_BLACKFIN_SIGNAL_H
#define _UAPI_BLACKFIN_SIGNAL_H
#define SA_RESTORER 0x04000000
#include <asm-generic/signal.h>
#endif
#endif /* _UAPI_BLACKFIN_SIGNAL_H */

6
arch/blackfin/include/uapi/asm/stat.h
View File

@ -4,8 +4,8 @@
* Licensed under the GPL-2.
*/
#ifndef _BFIN_STAT_H
#define _BFIN_STAT_H
#ifndef _UAPI_BFIN_STAT_H
#define _UAPI_BFIN_STAT_H
struct stat {
unsigned short st_dev;
@ -66,4 +66,4 @@ struct stat64 {
unsigned long long st_ino;
};
#endif /* _BFIN_STAT_H */
#endif /* _UAPI_BFIN_STAT_H */

6
arch/blackfin/include/uapi/asm/swab.h
View File

@ -4,8 +4,8 @@
* Licensed under the GPL-2 or later.
*/
#ifndef _BLACKFIN_SWAB_H
#define _BLACKFIN_SWAB_H
#ifndef _UAPI_BLACKFIN_SWAB_H
#define _UAPI_BLACKFIN_SWAB_H
#include <linux/types.h>
#include <asm-generic/swab.h>
@ -47,4 +47,4 @@ static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx)
#endif /* __GNUC__ */
#endif /* _BLACKFIN_SWAB_H */
#endif /* _UAPI_BLACKFIN_SWAB_H */

47
arch/blackfin/mach-bf533/boards/stamp.c
View File

@ -370,7 +370,8 @@ static struct platform_device bfin_sir0_device = {
#endif
#endif
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
#if defined(CONFIG_SERIAL_BFIN_SPORT) || \
defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
static struct resource bfin_sport0_uart_resources[] = {
{
@ -441,6 +442,50 @@ static struct platform_device bfin_sport1_uart_device = {
#endif
#endif
#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
static struct resource bfin_sport0_resources[] = {
{
.start = SPORT0_TCR1,
.end = SPORT0_MRCS3+4,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_SPORT0_TX,
.end = IRQ_SPORT0_TX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_SPORT0_RX,
.end = IRQ_SPORT0_RX+1,
.flags = IORESOURCE_IRQ,
},
{
.start = IRQ_SPORT0_ERROR,
.end = IRQ_SPORT0_ERROR,
.flags = IORESOURCE_IRQ,
},
{
.start = CH_SPORT0_TX,
.end = CH_SPORT0_TX,
.flags = IORESOURCE_DMA,
},
{
.start = CH_SPORT0_RX,
.end = CH_SPORT0_RX,
.flags = IORESOURCE_DMA,
},
};
static struct platform_device bfin_sport0_device = {
.name = "bfin_sport_raw",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_sport0_resources),
.resource = bfin_sport0_resources,
.dev = {
.platform_data = &bfin_sport0_peripherals,
},
};
#endif
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/input.h>
#include <linux/gpio_keys.h>

6
arch/blackfin/mach-bf609/Kconfig
View File

@ -17,6 +17,12 @@ config SEC_IRQ_PRIORITY_LEVELS
Divide the total number of interrupt priority levels into sub-levels.
There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
config L1_PARITY_CHECK
bool "Enable L1 parity check"
default n
help
Enable the L1 parity check in L1 sram. A fault event is raised
when L1 parity error is found.
comment "System Cross Bar Priority Assignment"

3
arch/blackfin/mach-bf609/clock.c
View File

@ -120,6 +120,7 @@ void clk_disable(struct clk *clk)
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long ret = 0;
@ -131,7 +132,7 @@ EXPORT_SYMBOL(clk_get_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
long ret = -EIO;
long ret = 0;
if (clk->ops && clk->ops->round_rate)
ret = clk->ops->round_rate(clk, rate);
return ret;

54
arch/blackfin/mach-bf609/include/mach/anomaly.h
View File

@ -23,11 +23,11 @@
/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
#define ANOMALY_16000003 (1)
/* The EPPI Data Enable (DEN) Signal is Not Functional */
#define ANOMALY_16000004 (1)
#define ANOMALY_16000004 (__SILICON_REVISION__ < 1)
/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
#define ANOMALY_16000005 (1)
#define ANOMALY_16000005 (__SILICON_REVISION__ < 1)
/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
#define ANOMALY_16000006 (1)
#define ANOMALY_16000006 (__SILICON_REVISION__ < 1)
/* DDR2 Memory Reads May Fail Intermittently */
#define ANOMALY_16000007 (1)
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
@ -49,19 +49,53 @@
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_16000017 (1)
/* RSI Boot Cleanup Routine Does Not Clear Registers */
#define ANOMALY_16000018 (1)
#define ANOMALY_16000018 (__SILICON_REVISION__ < 1)
/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
#define ANOMALY_16000019 (1)
#define ANOMALY_16000019 (__SILICON_REVISION__ < 1)
/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
#define ANOMALY_16000020 (1)
#define ANOMALY_16000020 (__SILICON_REVISION__ < 1)
/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
#define ANOMALY_16000021 (1)
#define ANOMALY_16000021 (__SILICON_REVISION__ < 1)
/* Boot Code Fails to Enable Parity Fault Detection */
#define ANOMALY_16000022 (1)
#define ANOMALY_16000022 (__SILICON_REVISION__ < 1)
/* Rom_SysControl Does not Update CGU0_CLKOUTSEL */
#define ANOMALY_16000023 (__SILICON_REVISION__ < 1)
/* Spurious Fault Signaled After Clearing an Externally Generated Fault */
#define ANOMALY_16000024 (1)
/* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */
#define ANOMALY_16000025 (1)
/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
#define ANOMALY_16000027 (1)
#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
/* Default SPI Master Boot Mode Setting is Incorrect */
#define ANOMALY_16000028 (__SILICON_REVISION__ < 1)
/* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */
#define ANOMALY_16000027 (__SILICON_REVISION__ < 1)
/* Interrupted Core Reads of MMRs May Cause Data Loss */
#define ANOMALY_16000030 (1)
#define ANOMALY_16000030 (__SILICON_REVISION__ < 1)
/* Incorrect Default USB_PLL_OSC.PLLM Value */
#define ANOMALY_16000031 (__SILICON_REVISION__ < 1)
/* Core Reads of System MMRs May Cause the Core to Hang */
#define ANOMALY_16000032 (__SILICON_REVISION__ < 1)
/* PPI Data Underflow on First Word Not Reported in Certain Modes */
#define ANOMALY_16000033 (1)
/* CNV1 Red Pixel Substitution feature not functional in the PVP */
#define ANOMALY_16000034 (__SILICON_REVISION__ < 1)
/* IPF0 Output Port Color Separation feature not functional */
#define ANOMALY_16000035 (__SILICON_REVISION__ < 1)
/* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */
#define ANOMALY_16000036 (__SILICON_REVISION__ < 1)
/* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */
#define ANOMALY_16000037 (__SILICON_REVISION__ < 1)
/* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */
#define ANOMALY_16000038 (__SILICON_REVISION__ < 1)
/* CGU_STAT.PLOCKERR Bit May be Unreliable */
#define ANOMALY_16000039 (1)
/* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */
#define ANOMALY_16000040 (1)
/* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */
#define ANOMALY_16000041 (1)
/* Instruction Cache Failure When Parity Is Enabled */
#define ANOMALY_16000042 (__SILICON_REVISION__ == 1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000158 (0)

11
arch/blackfin/mach-common/cache-c.c
View File

@ -6,7 +6,6 @@
* Licensed under the GPL-2 or later.
*/
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/cplbinit.h>
@ -42,6 +41,16 @@ bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
unsigned long mem_mask)
{
int i;
#ifdef CONFIG_L1_PARITY_CHECK
u32 ctrl;
if (cplb_addr == DCPLB_ADDR0) {
ctrl = bfin_read32(mem_control) | (1 << RDCHK);
CSYNC();
bfin_write32(mem_control, ctrl);
SSYNC();
}
#endif
for (i = 0; i < MAX_CPLBS; i++) {
bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);

1
arch/blackfin/mach-common/clocks-init.c
View File

@ -7,7 +7,6 @@
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/blackfin.h>
#include <asm/dma.h>

41
arch/blackfin/mach-common/ints-priority.c
View File

@ -471,13 +471,8 @@ void handle_sec_ssi_fault(uint32_t gstat)
}
void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
void handle_sec_fault(uint32_t sec_gstat)
{
uint32_t sec_gstat;
raw_spin_lock(&desc->lock);
sec_gstat = bfin_read32(SEC_GSTAT);
if (sec_gstat & SEC_GSTAT_ERR) {
switch (sec_gstat & SEC_GSTAT_ERRC) {
@ -494,18 +489,16 @@ void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
}
raw_spin_unlock(&desc->lock);
handle_fasteoi_irq(irq, desc);
}
void handle_core_fault(unsigned int irq, struct irq_desc *desc)
static struct irqaction bfin_fault_irq = {
.name = "Blackfin fault",
};
static irqreturn_t bfin_fault_routine(int irq, void *data)
{
struct pt_regs *fp = get_irq_regs();
raw_spin_lock(&desc->lock);
switch (irq) {
case IRQ_C0_DBL_FAULT:
double_fault_c(fp);
@ -522,11 +515,15 @@ void handle_core_fault(unsigned int irq, struct irq_desc *desc)
case IRQ_C0_NMI_L1_PARITY_ERR:
panic("Core 0 NMI L1 parity error");
break;
case IRQ_SEC_ERR:
pr_err("SEC error\n");
handle_sec_fault(bfin_read32(SEC_GSTAT));
break;
default:
panic("Core 1 fault %d occurs unexpectedly", irq);
panic("Unknown fault %d", irq);
}
raw_spin_unlock(&desc->lock);
return IRQ_HANDLED;
}
#endif /* SEC_GCTL */
@ -1195,12 +1192,7 @@ int __init init_arch_irq(void)
handle_percpu_irq);
} else {
irq_set_chip(irq, &bfin_sec_irqchip);
if (irq == IRQ_SEC_ERR)
irq_set_handler(irq, handle_sec_fault);
else if (irq >= IRQ_C0_DBL_FAULT && irq < CORE_IRQS)
irq_set_handler(irq, handle_core_fault);
else
irq_set_handler(irq, handle_fasteoi_irq);
irq_set_handler(irq, handle_fasteoi_irq);
__irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
}
}
@ -1239,6 +1231,13 @@ int __init init_arch_irq(void)
register_syscore_ops(&sec_pm_syscore_ops);
#endif
bfin_fault_irq.handler = bfin_fault_routine;
#ifdef CONFIG_L1_PARITY_CHECK
setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
#endif
setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
return 0;
}

1
arch/blackfin/mach-common/scb-init.c
View File

@ -6,7 +6,6 @@
* Licensed under the GPL-2 or later.
*/
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <asm/scb.h>

6
arch/blackfin/mach-common/smp.c
View File

@ -53,7 +53,6 @@ enum ipi_message_type {
BFIN_IPI_TIMER,
BFIN_IPI_RESCHEDULE,
BFIN_IPI_CALL_FUNC,
BFIN_IPI_CALL_FUNC_SINGLE,
BFIN_IPI_CPU_STOP,
};
@ -162,9 +161,6 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
case BFIN_IPI_CALL_FUNC:
generic_smp_call_function_interrupt();
break;
case BFIN_IPI_CALL_FUNC_SINGLE:
generic_smp_call_function_single_interrupt();
break;
case BFIN_IPI_CPU_STOP:
ipi_cpu_stop(cpu);
break;
@ -210,7 +206,7 @@ void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
void arch_send_call_function_single_ipi(int cpu)
{
send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC_SINGLE);
send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC);
}
void arch_send_call_function_ipi_mask(const struct cpumask *mask)