UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'kconfig_fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-next into kbuild/rc-fixes

This commit is contained in:
Michal Marek 2010-12-01 13:13:56 +01:00
parent 1198c6d45a 9b4320b77b
commit 307991055b
692 changed files with 11798 additions and 6145 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
Documentation/ABI/obsolete/proc-pid-oom_adj Normal file
View File

@ -0,0 +1,22 @@
What: /proc/<pid>/oom_adj
When: August 2012
Why: /proc/<pid>/oom_adj allows userspace to influence the oom killer's
badness heuristic used to determine which task to kill when the kernel
is out of memory.
The badness heuristic has since been rewritten since the introduction of
this tunable such that its meaning is deprecated. The value was
implemented as a bitshift on a score generated by the badness()
function that did not have any precise units of measure. With the
rewrite, the score is given as a proportion of available memory to the
task allocating pages, so using a bitshift which grows the score
exponentially is, thus, impossible to tune with fine granularity.
A much more powerful interface, /proc/<pid>/oom_score_adj, was
introduced with the oom killer rewrite that allows users to increase or
decrease the badness() score linearly. This interface will replace
/proc/<pid>/oom_adj.
A warning will be emitted to the kernel log if an application uses this
deprecated interface. After it is printed once, future warnings will be
suppressed until the kernel is rebooted.

7
Documentation/arm/OMAP/DSS
View File

@ -255,9 +255,10 @@ framebuffer parameters.
Kernel boot arguments
---------------------
vram=<size>
- Amount of total VRAM to preallocate. For example, "10M". omapfb
allocates memory for framebuffers from VRAM.
vram=<size>[,<physaddr>]
- Amount of total VRAM to preallocate and optionally a physical start
memory address. For example, "10M". omapfb allocates memory for
framebuffers from VRAM.
omapfb.mode=<display>:<mode>[,...]
- Default video mode for specified displays. For example,

8
Documentation/block/switching-sched.txt
View File

@ -16,7 +16,7 @@ you can do so by typing:
As of the Linux 2.6.10 kernel, it is now possible to change the
IO scheduler for a given block device on the fly (thus making it possible,
for instance, to set the CFQ scheduler for the system default, but
set a specific device to use the anticipatory or noop schedulers - which
set a specific device to use the deadline or noop schedulers - which
can improve that device's throughput).
To set a specific scheduler, simply do this:
@ -31,7 +31,7 @@ a "cat /sys/block/DEV/queue/scheduler" - the list of valid names
will be displayed, with the currently selected scheduler in brackets:
# cat /sys/block/hda/queue/scheduler
noop anticipatory deadline [cfq]
# echo anticipatory > /sys/block/hda/queue/scheduler
noop deadline [cfq]
# echo deadline > /sys/block/hda/queue/scheduler
# cat /sys/block/hda/queue/scheduler
noop [anticipatory] deadline cfq
noop [deadline] cfq

10
Documentation/feature-removal-schedule.txt
View File

@ -554,3 +554,13 @@ Why: This is a legacy interface which have been replaced by a more
Who: NeilBrown <neilb@suse.de>
----------------------------
What: i2c_adapter.id
When: June 2011
Why: This field is deprecated. I2C device drivers shouldn't change their
behavior based on the underlying I2C adapter. Instead, the I2C
adapter driver should instantiate the I2C devices and provide the
needed platform-specific information.
Who: Jean Delvare <khali@linux-fr.org>
----------------------------

11
Documentation/filesystems/xfs-delayed-logging-design.txt
View File

@ -794,17 +794,6 @@ designed.
Roadmap:
2.6.37 Remove experimental tag from mount option
=> should be roughly 6 months after initial merge
=> enough time to:
=> gain confidence and fix problems reported by early
adopters (a.k.a. guinea pigs)
=> address worst performance regressions and undesired
behaviours
=> start tuning/optimising code for parallelism
=> start tuning/optimising algorithms consuming
excessive CPU time
2.6.39 Switch default mount option to use delayed logging
=> should be roughly 12 months after initial merge
=> enough time to shake out remaining problems before next round of

2
Documentation/kernel-parameters.txt
View File

@ -706,7 +706,7 @@ and is between 256 and 4096 characters. It is defined in the file
arch/x86/kernel/cpu/cpufreq/elanfreq.c.
elevator= [IOSCHED]
Format: {"anticipatory" | "cfq" | "deadline" | "noop"}
Format: {"cfq" | "deadline" | "noop"}
See Documentation/block/as-iosched.txt and
Documentation/block/deadline-iosched.txt for details.

19
Documentation/leds-class.txt
View File

@ -60,15 +60,18 @@ Hardware accelerated blink of LEDs
Some LEDs can be programmed to blink without any CPU interaction. To
support this feature, a LED driver can optionally implement the
blink_set() function (see <linux/leds.h>). If implemented, triggers can
attempt to use it before falling back to software timers. The blink_set()
function should return 0 if the blink setting is supported, or -EINVAL
otherwise, which means that LED blinking will be handled by software.
blink_set() function (see <linux/leds.h>). To set an LED to blinking,
however, it is better to use use the API function led_blink_set(),
as it will check and implement software fallback if necessary.
The blink_set() function should choose a user friendly blinking
value if it is called with *delay_on==0 && *delay_off==0 parameters. In
this case the driver should give back the chosen value through delay_on
and delay_off parameters to the leds subsystem.
To turn off blinking again, use the API function led_brightness_set()
as that will not just set the LED brightness but also stop any software
timers that may have been required for blinking.
The blink_set() function should choose a user friendly blinking value
if it is called with *delay_on==0 && *delay_off==0 parameters. In this
case the driver should give back the chosen value through delay_on and
delay_off parameters to the leds subsystem.
Setting the brightness to zero with brightness_set() callback function
should completely turn off the LED and cancel the previously programmed

88
Documentation/leds/leds-lp5521.txt Normal file
View File

@ -0,0 +1,88 @@
Kernel driver for lp5521
========================
* National Semiconductor LP5521 led driver chip
* Datasheet: http://www.national.com/pf/LP/LP5521.html
Authors: Mathias Nyman, Yuri Zaporozhets, Samu Onkalo
Contact: Samu Onkalo (samu.p.onkalo-at-nokia.com)
Description
-----------
LP5521 can drive up to 3 channels. Leds can be controlled directly via
the led class control interface. Channels have generic names:
lp5521:channelx, where x is 0 .. 2
All three channels can be also controlled using the engine micro programs.
More details of the instructions can be found from the public data sheet.
Control interface for the engines:
x is 1 .. 3
enginex_mode : disabled, load, run
enginex_load : store program (visible only in engine load mode)
Example (start to blink the channel 2 led):
cd /sys/class/leds/lp5521:channel2/device
echo "load" > engine3_mode
echo "037f4d0003ff6000" > engine3_load
echo "run" > engine3_mode
stop the engine:
echo "disabled" > engine3_mode
sysfs contains a selftest entry.
The test communicates with the chip and checks that
the clock mode is automatically set to the requested one.
Each channel has its own led current settings.
/sys/class/leds/lp5521:channel0/led_current - RW
/sys/class/leds/lp5521:channel0/max_current - RO
Format: 10x mA i.e 10 means 1.0 mA
example platform data:
Note: chan_nr can have values between 0 and 2.
static struct lp5521_led_config lp5521_led_config[] = {
{
.chan_nr = 0,
.led_current = 50,
.max_current = 130,
}, {
.chan_nr = 1,
.led_current = 0,
.max_current = 130,
}, {
.chan_nr = 2,
.led_current = 0,
.max_current = 130,
}
};
static int lp5521_setup(void)
{
/* setup HW resources */
}
static void lp5521_release(void)
{
/* Release HW resources */
}
static void lp5521_enable(bool state)
{
/* Control of chip enable signal */
}
static struct lp5521_platform_data lp5521_platform_data = {
.led_config = lp5521_led_config,
.num_channels = ARRAY_SIZE(lp5521_led_config),
.clock_mode = LP5521_CLOCK_EXT,
.setup_resources = lp5521_setup,
.release_resources = lp5521_release,
.enable = lp5521_enable,
};
If the current is set to 0 in the platform data, that channel is
disabled and it is not visible in the sysfs.

83
Documentation/leds/leds-lp5523.txt Normal file
View File

@ -0,0 +1,83 @@
Kernel driver for lp5523
========================
* National Semiconductor LP5523 led driver chip
* Datasheet: http://www.national.com/pf/LP/LP5523.html
Authors: Mathias Nyman, Yuri Zaporozhets, Samu Onkalo
Contact: Samu Onkalo (samu.p.onkalo-at-nokia.com)
Description
-----------
LP5523 can drive up to 9 channels. Leds can be controlled directly via
the led class control interface. Channels have generic names:
lp5523:channelx where x is 0...8
The chip provides 3 engines. Each engine can control channels without
interaction from the main CPU. Details of the micro engine code can be found
from the public data sheet. Leds can be muxed to different channels.
Control interface for the engines:
x is 1 .. 3
enginex_mode : disabled, load, run
enginex_load : microcode load (visible only in load mode)
enginex_leds : led mux control (visible only in load mode)
cd /sys/class/leds/lp5523:channel2/device
echo "load" > engine3_mode
echo "9d80400004ff05ff437f0000" > engine3_load
echo "111111111" > engine3_leds
echo "run" > engine3_mode
sysfs contains a selftest entry. It measures each channel
voltage level and checks if it looks reasonable. If the level is too high,
the led is missing; if the level is too low, there is a short circuit.
Selftest uses always the current from the platform data.
Each channel contains led current settings.
/sys/class/leds/lp5523:channel2/led_current - RW
/sys/class/leds/lp5523:channel2/max_current - RO
Format: 10x mA i.e 10 means 1.0 mA
Example platform data:
Note - chan_nr can have values between 0 and 8.
static struct lp5523_led_config lp5523_led_config[] = {
{
.chan_nr = 0,
.led_current = 50,
.max_current = 130,
},
...
}, {
.chan_nr = 8,
.led_current = 50,
.max_current = 130,
}
};
static int lp5523_setup(void)
{
/* Setup HW resources */
}
static void lp5523_release(void)
{
/* Release HW resources */
}
static void lp5523_enable(bool state)
{
/* Control chip enable signal */
}
static struct lp5523_platform_data lp5523_platform_data = {
.led_config = lp5523_led_config,
.num_channels = ARRAY_SIZE(lp5523_led_config),
.clock_mode = LP5523_CLOCK_EXT,
.setup_resources = lp5523_setup,
.release_resources = lp5523_release,
.enable = lp5523_enable,
};

9
Documentation/networking/ip-sysctl.txt
View File

@ -20,6 +20,15 @@ ip_no_pmtu_disc - BOOLEAN
min_pmtu - INTEGER
default 562 - minimum discovered Path MTU
route/max_size - INTEGER
Maximum number of routes allowed in the kernel. Increase
this when using large numbers of interfaces and/or routes.
neigh/default/gc_thresh3 - INTEGER
Maximum number of neighbor entries allowed. Increase this
when using large numbers of interfaces and when communicating
with large numbers of directly-connected peers.
mtu_expires - INTEGER
Time, in seconds, that cached PMTU information is kept.

4
Documentation/rbtree.txt
View File

@ -21,8 +21,8 @@ three rotations, respectively, to balance the tree), with slightly slower
To quote Linux Weekly News:
There are a number of red-black trees in use in the kernel.
The anticipatory, deadline, and CFQ I/O schedulers all employ
rbtrees to track requests; the packet CD/DVD driver does the same.
The deadline and CFQ I/O schedulers employ rbtrees to
track requests; the packet CD/DVD driver does the same.
The high-resolution timer code uses an rbtree to organize outstanding
timer requests. The ext3 filesystem tracks directory entries in a
red-black tree. Virtual memory areas (VMAs) are tracked with red-black

14
Documentation/sysctl/kernel.txt
View File

@ -28,6 +28,7 @@ show up in /proc/sys/kernel:
- core_uses_pid
- ctrl-alt-del
- dentry-state
- dmesg_restrict
- domainname
- hostname
- hotplug
@ -213,6 +214,19 @@ to decide what to do with it.
==============================================================
dmesg_restrict:
This toggle indicates whether unprivileged users are prevented from using
dmesg(8) to view messages from the kernel's log buffer. When
dmesg_restrict is set to (0) there are no restrictions. When
dmesg_restrict is set set to (1), users must have CAP_SYS_ADMIN to use
dmesg(8).
The kernel config option CONFIG_SECURITY_DMESG_RESTRICT sets the default
value of dmesg_restrict.
==============================================================
domainname & hostname:
These files can be used to set the NIS/YP domainname and the

19
MAINTAINERS
View File

@ -161,7 +161,7 @@ M: Greg Kroah-Hartman <gregkh@suse.de>
L: linux-serial@vger.kernel.org
W: http://serial.sourceforge.net
S: Maintained
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git
F: drivers/serial/8250*
F: include/linux/serial_8250.h
@ -945,7 +945,7 @@ M: Magnus Damm <magnus.damm@gmail.com>
L: linux-sh@vger.kernel.org
W: http://oss.renesas.com
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/genesis-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git rmobile-latest
S: Supported
F: arch/arm/mach-shmobile/
F: drivers/sh/
@ -2435,6 +2435,7 @@ F: drivers/net/wan/sdla.c
FRAMEBUFFER LAYER
L: linux-fbdev@vger.kernel.org
W: http://linux-fbdev.sourceforge.net/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/fbdev-2.6.git
S: Orphan
F: Documentation/fb/
F: drivers/video/fb*
@ -5676,7 +5677,7 @@ S: Maintained
STAGING SUBSYSTEM
M: Greg Kroah-Hartman <gregkh@suse.de>
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-next-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6.git
L: devel@driverdev.osuosl.org
S: Maintained
F: drivers/staging/
@ -5705,7 +5706,7 @@ M: Paul Mundt <lethal@linux-sh.org>
L: linux-sh@vger.kernel.org
W: http://www.linux-sh.org
Q: http://patchwork.kernel.org/project/linux-sh/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6.git sh-latest
S: Supported
F: Documentation/sh/
F: arch/sh/
@ -5910,7 +5911,7 @@ S: Maintained
TTY LAYER
M: Greg Kroah-Hartman <gregkh@suse.de>
S: Maintained
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git
F: drivers/char/tty_*
F: drivers/serial/serial_core.c
F: include/linux/serial_core.h
@ -6233,7 +6234,7 @@ USB SUBSYSTEM
M: Greg Kroah-Hartman <gregkh@suse.de>
L: linux-usb@vger.kernel.org
W: http://www.linux-usb.org
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6.git
S: Supported
F: Documentation/usb/
F: drivers/net/usb/
@ -6598,14 +6599,14 @@ F: drivers/platform/x86
XEN PCI SUBSYSTEM
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
L: xen-devel@lists.xensource.com
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
S: Supported
F: arch/x86/pci/*xen*
F: drivers/pci/*xen*
XEN SWIOTLB SUBSYSTEM
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
L: xen-devel@lists.xensource.com
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
S: Supported
F: arch/x86/xen/*swiotlb*
F: drivers/xen/*swiotlb*
@ -6613,7 +6614,7 @@ F: drivers/xen/*swiotlb*
XEN HYPERVISOR INTERFACE
M: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
L: xen-devel@lists.xen.org
L: xen-devel@lists.xensource.com (moderated for non-subscribers)
L: virtualization@lists.osdl.org
S: Supported
F: arch/x86/xen/

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 37
EXTRAVERSION = -rc1
EXTRAVERSION = -rc2
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*

34
arch/arm/Kconfig
View File

@ -6,7 +6,7 @@ config ARM
select HAVE_MEMBLOCK
select RTC_LIB
select SYS_SUPPORTS_APM_EMULATION
select GENERIC_ATOMIC64 if (!CPU_32v6K)
select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
@ -646,7 +646,7 @@ config ARCH_S3C2410
select ARCH_HAS_CPUFREQ
select HAVE_CLK
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C2410_I2C if I2C
help
Samsung S3C2410X CPU based systems, such as the Simtec Electronics
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
@ -676,8 +676,8 @@ config ARCH_S3C64XX
select S3C_DEV_NAND
select USB_ARCH_HAS_OHCI
select SAMSUNG_GPIOLIB_4BIT
select HAVE_S3C2410_I2C
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S3C64XX series based systems
@ -686,10 +686,10 @@ config ARCH_S5P64X0
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
help
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
@ -700,7 +700,7 @@ config ARCH_S5P6442
select GENERIC_GPIO
select HAVE_CLK
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5P6442 CPU based systems
@ -711,9 +711,9 @@ config ARCH_S5PC100
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PC100 series based systems
@ -726,9 +726,9 @@ config ARCH_S5PV210
select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PV210/S5PC110 series based systems
@ -739,9 +739,9 @@ config ARCH_S5PV310
select GENERIC_GPIO
select HAVE_CLK
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC
select HAVE_S3C2410_I2C
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PV310 series based systems

28
arch/arm/common/gic.c
View File

@ -251,15 +251,16 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
/*
* Set priority on all interrupts.
* Set priority on all global interrupts.
*/
for (i = 0; i < max_irq; i += 4)
for (i = 32; i < max_irq; i += 4)
writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
/*
* Disable all interrupts.
* Disable all interrupts. Leave the PPI and SGIs alone
* as these enables are banked registers.
*/
for (i = 0; i < max_irq; i += 32)
for (i = 32; i < max_irq; i += 32)
writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
@ -277,11 +278,30 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
{
void __iomem *dist_base;
int i;
if (gic_nr >= MAX_GIC_NR)
BUG();
dist_base = gic_data[gic_nr].dist_base;
BUG_ON(!dist_base);
gic_data[gic_nr].cpu_base = base;
/*
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
/*
* Set priority on PPI and SGI interrupts
*/
for (i = 0; i < 32; i += 4)
writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
writel(0xf0, base + GIC_CPU_PRIMASK);
writel(1, base + GIC_CPU_CTRL);
}

2
arch/arm/include/asm/hardware/it8152.h
View File

@ -75,7 +75,7 @@ extern unsigned long it8152_base_address;
IT8152_PD_IRQ(1) USB (USBR)
IT8152_PD_IRQ(0) Audio controller (ACR)
*/
#define IT8152_IRQ(x) (IRQ_BOARD_END + (x))
#define IT8152_IRQ(x) (IRQ_BOARD_START + (x))
/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
#define IT8152_LD_IRQ_COUNT 9

3
arch/arm/kernel/hw_breakpoint.c
View File

@ -748,8 +748,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
breakpoint_handler(addr, regs);
break;
case ARM_ENTRY_ASYNC_WATCHPOINT:
WARN_ON("Asynchronous watchpoint exception taken. "
"Debugging results may be unreliable");
WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
case ARM_ENTRY_SYNC_WATCHPOINT:
watchpoint_handler(addr, regs);
break;

2
arch/arm/kernel/perf_event.c
View File

@ -1749,7 +1749,7 @@ static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
enum armv7_counters counter)
{
int ret;
int ret = 0;
if (counter == ARMV7_CYCLE_COUNTER)
ret = pmnc & ARMV7_FLAG_C;

2
arch/arm/kernel/stacktrace.c
View File

@ -28,7 +28,7 @@ int notrace unwind_frame(struct stackframe *frame)
/* only go to a higher address on the stack */
low = frame->sp;
high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
high = ALIGN(low, THREAD_SIZE);
/* check current frame pointer is within bounds */
if (fp < (low + 12) || fp + 4 >= high)

5
arch/arm/kernel/traps.c
View File

@ -53,10 +53,7 @@ static void dump_mem(const char *, const char *, unsigned long, unsigned long);
void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame)
{
#ifdef CONFIG_KALLSYMS
char sym1[KSYM_SYMBOL_LEN], sym2[KSYM_SYMBOL_LEN];
sprint_symbol(sym1, where);
sprint_symbol(sym2, from);
printk("[<%08lx>] (%s) from [<%08lx>] (%s)\n", where, sym1, from, sym2);
printk("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
#else
printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
#endif

2
arch/arm/kernel/unwind.c
View File

@ -279,7 +279,7 @@ int unwind_frame(struct stackframe *frame)
/* only go to a higher address on the stack */
low = frame->sp;
high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE;
high = ALIGN(low, THREAD_SIZE);
pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__,
frame->pc, frame->lr, frame->sp);

109
arch/arm/mach-ep93xx/include/mach/dma.h
View File

@ -1,5 +1,13 @@
/*
* arch/arm/mach-ep93xx/include/mach/dma.h
/**
* DOC: EP93xx DMA M2P memory to peripheral and peripheral to memory engine
*
* The EP93xx DMA M2P subsystem handles DMA transfers between memory and
* peripherals. DMA M2P channels are available for audio, UARTs and IrDA.
* See chapter 10 of the EP93xx users guide for full details on the DMA M2P
* engine.
*
* See sound/soc/ep93xx/ep93xx-pcm.c for an example use of the DMA M2P code.
*
*/
#ifndef __ASM_ARCH_DMA_H
@ -8,12 +16,34 @@
#include <linux/list.h>
#include <linux/types.h>
/**
* struct ep93xx_dma_buffer - Information about a buffer to be transferred
* using the DMA M2P engine
*
* @list: Entry in DMA buffer list
* @bus_addr: Physical address of the buffer
* @size: Size of the buffer in bytes
*/
struct ep93xx_dma_buffer {
struct list_head list;
u32 bus_addr;
u16 size;
};
/**
* struct ep93xx_dma_m2p_client - Information about a DMA M2P client
*
* @name: Unique name for this client
* @flags: Client flags
* @cookie: User data to pass to callback functions
* @buffer_started: Non NULL function to call when a transfer is started.
* The arguments are the user data cookie and the DMA
* buffer which is starting.
* @buffer_finished: Non NULL function to call when a transfer is completed.
* The arguments are the user data cookie, the DMA buffer
* which has completed, and a boolean flag indicating if
* the transfer had an error.
*/
struct ep93xx_dma_m2p_client {
char *name;
u8 flags;
@ -24,10 +54,11 @@ struct ep93xx_dma_m2p_client {
struct ep93xx_dma_buffer *buf,
int bytes, int error);
/* Internal to the DMA code. */
/* private: Internal use only */
void *channel;
};
/* DMA M2P ports */
#define EP93XX_DMA_M2P_PORT_I2S1 0x00
#define EP93XX_DMA_M2P_PORT_I2S2 0x01
#define EP93XX_DMA_M2P_PORT_AAC1 0x02
@ -39,18 +70,80 @@ struct ep93xx_dma_m2p_client {
#define EP93XX_DMA_M2P_PORT_UART3 0x08
#define EP93XX_DMA_M2P_PORT_IRDA 0x09
#define EP93XX_DMA_M2P_PORT_MASK 0x0f
#define EP93XX_DMA_M2P_TX 0x00
#define EP93XX_DMA_M2P_RX 0x10
#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20
#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40
#define EP93XX_DMA_M2P_ERROR_MASK 0x60
/* DMA M2P client flags */
#define EP93XX_DMA_M2P_TX 0x00 /* Memory to peripheral */
#define EP93XX_DMA_M2P_RX 0x10 /* Peripheral to memory */
/*
* DMA M2P client error handling flags. See the EP93xx users guide
* documentation on the DMA M2P CONTROL register for more details
*/
#define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20 /* Abort on peripheral error */
#define EP93XX_DMA_M2P_IGNORE_ERROR 0x40 /* Ignore peripheral errors */
#define EP93XX_DMA_M2P_ERROR_MASK 0x60 /* Mask of error bits */
/**
* ep93xx_dma_m2p_client_register - Register a client with the DMA M2P
* subsystem
*
* @m2p: Client information to register
* returns 0 on success
*
* The DMA M2P subsystem allocates a channel and an interrupt line for the DMA
* client
*/
int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p);
/**
* ep93xx_dma_m2p_client_unregister - Unregister a client from the DMA M2P
* subsystem
*
* @m2p: Client to unregister
*
* Any transfers currently in progress will be completed in hardware, but
* ignored in software.
*/
void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p);
/**
* ep93xx_dma_m2p_submit - Submit a DMA M2P transfer
*
* @m2p: DMA Client to submit the transfer on
* @buf: DMA Buffer to submit
*
* If the current or next transfer positions are free on the M2P client then
* the transfer is started immediately. If not, the transfer is added to the
* list of pending transfers. This function must not be called from the
* buffer_finished callback for an M2P channel.
*
*/
void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p,
struct ep93xx_dma_buffer *buf);
/**
* ep93xx_dma_m2p_submit_recursive - Put a DMA transfer on the pending list
* for an M2P channel
*
* @m2p: DMA Client to submit the transfer on
* @buf: DMA Buffer to submit
*
* This function must only be called from the buffer_finished callback for an
* M2P channel. It is commonly used to add the next transfer in a chained list
* of DMA transfers.
*/
void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p,
struct ep93xx_dma_buffer *buf);
/**
* ep93xx_dma_m2p_flush - Flush all pending transfers on a DMA M2P client
*
* @m2p: DMA client to flush transfers on
*
* Any transfers currently in progress will be completed in hardware, but
* ignored in software.
*
*/
void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p);
#endif /* __ASM_ARCH_DMA_H */

5
arch/arm/mach-kirkwood/common.c
View File

@ -854,9 +854,8 @@ int __init kirkwood_find_tclk(void)
kirkwood_pcie_id(&dev, &rev);
if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
rev == MV88F6281_REV_A1)) ||
(dev == MV88F6282_DEV_ID))
if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
return 200000000;
return 166666667;

2
arch/arm/mach-kirkwood/d2net_v2-setup.c
View File

@ -225,5 +225,5 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
.init_machine = d2net_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END

14
arch/arm/mach-kirkwood/lacie_v2-common.c
View File

@ -111,17 +111,3 @@ void __init lacie_v2_hdd_power_init(int hdd_num)
pr_err("Failed to power up HDD%d\n", i + 1);
}
}
/*****************************************************************************
* Timer
****************************************************************************/
static void lacie_v2_timer_init(void)
{
kirkwood_tclk = 166666667;
orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
struct sys_timer lacie_v2_timer = {
.init = lacie_v2_timer_init,
};

2
arch/arm/mach-kirkwood/lacie_v2-common.h
View File

@ -13,6 +13,4 @@ void lacie_v2_register_flash(void);
void lacie_v2_register_i2c_devices(void);
void lacie_v2_hdd_power_init(int hdd_num);
extern struct sys_timer lacie_v2_timer;
#endif

4
arch/arm/mach-kirkwood/mpp.c
View File

@ -59,7 +59,7 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
}
printk("\n");
while (*mpp_list) {
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
@ -88,8 +88,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
mpp_list++;
}
printk(KERN_DEBUG " final MPP regs:");

6
arch/arm/mach-kirkwood/netspace_v2-setup.c
View File

@ -262,7 +262,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif
@ -272,7 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif
@ -282,6 +282,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif

4
arch/arm/mach-kirkwood/netxbig_v2-setup.c
View File

@ -403,7 +403,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif
@ -413,6 +413,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
.timer = &kirkwood_timer,
MACHINE_END
#endif

14
arch/arm/mach-kirkwood/ts41x-setup.c
View File

@ -27,6 +27,10 @@
#include "mpp.h"
#include "tsx1x-common.h"
/* for the PCIe reset workaround */
#include <plat/pcie.h>
#define QNAP_TS41X_JUMPER_JP1 45
static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
@ -140,8 +144,16 @@ static void __init qnap_ts41x_init(void)
static int __init ts41x_pci_init(void)
{
if (machine_is_ts41x())
if (machine_is_ts41x()) {
/*
* Without this explicit reset, the PCIe SATA controller
* (Marvell 88sx7042/sata_mv) is known to stop working
* after a few minutes.
*/
orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
kirkwood_pcie_init(KW_PCIE0);
}
return 0;
}

3
arch/arm/mach-mmp/include/mach/cputype.h
View File

@ -46,7 +46,8 @@ static inline int cpu_is_pxa910(void)
#ifdef CONFIG_CPU_MMP2
static inline int cpu_is_mmp2(void)
{
return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
return (((read_cpuid_id() >> 8) & 0xff) == 0x58);
}
#else
#define cpu_is_mmp2() (0)
#endif

4
arch/arm/mach-mv78xx0/mpp.c
View File

@ -54,7 +54,7 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
}
printk("\n");
while (*mpp_list) {
for ( ; *mpp_list; mpp_list++) {
unsigned int num = MPP_NUM(*mpp_list);
unsigned int sel = MPP_SEL(*mpp_list);
int shift, gpio_mode;
@ -83,8 +83,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
if (sel != 0)
gpio_mode = 0;
orion_gpio_set_valid(num, gpio_mode);
mpp_list++;
}
printk(KERN_DEBUG " final MPP regs:");

5
arch/arm/mach-omap1/devices.c
View File

@ -321,10 +321,9 @@ static struct platform_device omap_wdt_device = {
static int __init omap_init_wdt(void)
{
if (!cpu_is_omap16xx())
return;
return -ENODEV;
platform_device_register(&omap_wdt_device);
return 0;
return platform_device_register(&omap_wdt_device);
}
subsys_initcall(omap_init_wdt);
#endif

2
arch/arm/mach-omap1/include/mach/camera.h
View File

@ -1,6 +1,8 @@
#ifndef __ASM_ARCH_CAMERA_H_
#define __ASM_ARCH_CAMERA_H_
#include <media/omap1_camera.h>
void omap1_camera_init(void *);
static inline void omap1_set_camera_info(struct omap1_cam_platform_data *info)

3
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -242,9 +242,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
/* link regulators to MMC adapters */
devkit8000_vmmc1_supply.dev = mmc[0].dev;
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;

4
arch/arm/mach-orion5x/mpp.c
View File

@ -127,7 +127,7 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
/* Initialize gpiolib. */
orion_gpio_init();
while (mode->mpp >= 0) {
for ( ; mode->mpp >= 0; mode++) {
u32 *reg;
int num_type;
int shift;
@ -160,8 +160,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
orion_gpio_set_unused(mode->mpp);
orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
mode++;
}
writel(mpp_0_7_ctrl, MPP_0_7_CTRL);

2
arch/arm/mach-orion5x/ts78xx-setup.c
View File

@ -239,7 +239,7 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
static struct resource ts78xx_ts_nand_resources = {
.start = TS_NAND_DATA,
.end = TS_NAND_DATA + 4,
.flags = IORESOURCE_IO,
.flags = IORESOURCE_MEM,
};
static struct platform_device ts78xx_ts_nand_device = {

2
arch/arm/mach-pxa/cm-x2xx.c
View File

@ -476,8 +476,6 @@ static void __init cmx2xx_init(void)
static void __init cmx2xx_init_irq(void)
{
pxa27x_init_irq();
if (cpu_is_pxa25x()) {
pxa25x_init_irq();
cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);

2
arch/arm/mach-pxa/saar.c
View File

@ -116,7 +116,7 @@ static struct platform_device smc91x_device = {
},
};
#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULE)
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static uint16_t lcd_power_on[] = {
/* single frame */
SMART_CMD_NOOP,

2
arch/arm/mach-s3c64xx/Kconfig
View File

@ -143,7 +143,7 @@ config MACH_SMDK6410
select S3C_DEV_USB_HSOTG
select S3C_DEV_WDT
select SAMSUNG_DEV_KEYPAD
select HAVE_S3C2410_WATCHDOG
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select S3C64XX_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_IDE

2
arch/arm/mach-shmobile/Kconfig
View File

@ -116,4 +116,6 @@ endmenu
config SH_CLK_CPG
bool
source "drivers/sh/Kconfig"
endif

52
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -163,11 +163,13 @@ static struct mtd_partition nor_flash_partitions[] = {
.name = "loader",
.offset = 0x00000000,
.size = 512 * 1024,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "bootenv",
.offset = MTDPART_OFS_APPEND,
.size = 512 * 1024,
.mask_flags = MTD_WRITEABLE,
},
{
.name = "kernel_ro",
@ -565,12 +567,54 @@ static struct platform_device *qhd_devices[] __initdata = {
/* FSI */
#define IRQ_FSI evt2irq(0x1840)
static int fsi_set_rate(int is_porta, int rate)
{
struct clk *fsib_clk;
struct clk *fdiv_clk = &sh7372_fsidivb_clk;
int ret;
/* set_rate is not needed if port A */
if (is_porta)
return 0;
fsib_clk = clk_get(NULL, "fsib_clk");
if (IS_ERR(fsib_clk))
return -EINVAL;
switch (rate) {
case 44100:
clk_set_rate(fsib_clk, clk_round_rate(fsib_clk, 11283000));
ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
break;
case 48000:
clk_set_rate(fsib_clk, clk_round_rate(fsib_clk, 85428000));
clk_set_rate(fdiv_clk, clk_round_rate(fdiv_clk, 12204000));
ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
break;
default:
pr_err("unsupported rate in FSI2 port B\n");
ret = -EINVAL;
break;
}
clk_put(fsib_clk);
return ret;
}
static struct sh_fsi_platform_info fsi_info = {
.porta_flags = SH_FSI_BRS_INV |
SH_FSI_OUT_SLAVE_MODE |
SH_FSI_IN_SLAVE_MODE |
SH_FSI_OFMT(PCM) |
SH_FSI_IFMT(PCM),
.portb_flags = SH_FSI_BRS_INV |
SH_FSI_BRM_INV |
SH_FSI_LRS_INV |
SH_FSI_OFMT(SPDIF),
.set_rate = fsi_set_rate,
};
static struct resource fsi_resources[] = {
@ -634,6 +678,7 @@ static struct platform_device lcdc1_device = {
static struct sh_mobile_hdmi_info hdmi_info = {
.lcd_chan = &sh_mobile_lcdc1_info.ch[0],
.lcd_dev = &lcdc1_device.dev,
.flags = HDMI_SND_SRC_SPDIF,
};
static struct resource hdmi_resources[] = {
@ -992,6 +1037,7 @@ static void __init ap4evb_map_io(void)
#define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A
#define USCCR1 0xE6058144
static void __init ap4evb_init(void)
{
u32 srcr4;
@ -1062,7 +1108,7 @@ static void __init ap4evb_init(void)
/* setup USB phy */
__raw_writew(0x8a0a, 0xE6058130); /* USBCR2 */
/* enable FSI2 */
/* enable FSI2 port A (ak4643) */
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
@ -1079,6 +1125,10 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_PORT41, NULL);
gpio_direction_input(GPIO_PORT41);
/* setup FSI2 port B (HDMI) */
gpio_request(GPIO_FN_FSIBCK, NULL);
__raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
/* set SPU2 clock to 119.6 MHz */
clk = clk_get(NULL, "spu_clk");
if (!IS_ERR(clk)) {

102
arch/arm/mach-shmobile/clock-sh7372.c
View File

@ -50,6 +50,9 @@
#define SMSTPCR3 0xe615013c
#define SMSTPCR4 0xe6150140
#define FSIDIVA 0xFE1F8000
#define FSIDIVB 0xFE1F8008
/* Platforms must set frequency on their DV_CLKI pin */
struct clk sh7372_dv_clki_clk = {
};
@ -288,6 +291,7 @@ struct clk sh7372_pllc2_clk = {
.ops = &pllc2_clk_ops,
.parent = &extal1_div2_clk,
.freq_table = pllc2_freq_table,
.nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1,
.parent_table = pllc2_parent,
.parent_num = ARRAY_SIZE(pllc2_parent),
};
@ -417,6 +421,101 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
};
/* FSI DIV */
static unsigned long fsidiv_recalc(struct clk *clk)
{
unsigned long value;
value = __raw_readl(clk->mapping->base);
if ((value & 0x3) != 0x3)
return 0;
value >>= 16;
if (value < 2)
return 0;
return clk->parent->rate / value;
}
static long fsidiv_round_rate(struct clk *clk, unsigned long rate)
{
return clk_rate_div_range_round(clk, 2, 0xffff, rate);
}
static void fsidiv_disable(struct clk *clk)
{
__raw_writel(0, clk->mapping->base);
}
static int fsidiv_enable(struct clk *clk)
{
unsigned long value;
value = __raw_readl(clk->mapping->base) >> 16;
if (value < 2) {
fsidiv_disable(clk);
return -ENOENT;
}
__raw_writel((value << 16) | 0x3, clk->mapping->base);
return 0;
}
static int fsidiv_set_rate(struct clk *clk,
unsigned long rate, int algo_id)
{
int idx;
if (clk->parent->rate == rate) {
fsidiv_disable(clk);
return 0;
}
idx = (clk->parent->rate / rate) & 0xffff;
if (idx < 2)
return -ENOENT;
__raw_writel(idx << 16, clk->mapping->base);
return fsidiv_enable(clk);
}
static struct clk_ops fsidiv_clk_ops = {
.recalc = fsidiv_recalc,
.round_rate = fsidiv_round_rate,
.set_rate = fsidiv_set_rate,
.enable = fsidiv_enable,
.disable = fsidiv_disable,
};
static struct clk_mapping sh7372_fsidiva_clk_mapping = {
.phys = FSIDIVA,
.len = 8,
};
struct clk sh7372_fsidiva_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
.mapping = &sh7372_fsidiva_clk_mapping,
};
static struct clk_mapping sh7372_fsidivb_clk_mapping = {
.phys = FSIDIVB,
.len = 8,
};
struct clk sh7372_fsidivb_clk = {
.ops = &fsidiv_clk_ops,
.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
.mapping = &sh7372_fsidivb_clk_mapping,
};
static struct clk *late_main_clks[] = {
&sh7372_fsidiva_clk,
&sh7372_fsidivb_clk,
};
enum { MSTP001,
MSTP131, MSTP130,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
@ -585,6 +684,9 @@ void __init sh7372_clock_init(void)
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)

4
arch/arm/mach-shmobile/include/mach/gpio.h
View File

@ -35,12 +35,12 @@ static inline int gpio_cansleep(unsigned gpio)
static inline int gpio_to_irq(unsigned gpio)
{
return -ENOSYS;
return __gpio_to_irq(gpio);
}
static inline int irq_to_gpio(unsigned int irq)
{
return -EINVAL;
return -ENOSYS;
}
#endif /* CONFIG_GPIOLIB */

2
arch/arm/mach-shmobile/include/mach/sh7372.h
View File

@ -464,5 +464,7 @@ extern struct clk sh7372_dv_clki_div2_clk;
extern struct clk sh7372_pllc2_clk;
extern struct clk sh7372_fsiack_clk;
extern struct clk sh7372_fsibck_clk;
extern struct clk sh7372_fsidiva_clk;
extern struct clk sh7372_fsidivb_clk;
#endif /* __ASM_SH7372_H__ */

2
arch/arm/mach-shmobile/intc-sh7372.c
View File

@ -98,7 +98,7 @@ static struct intc_vect intca_vectors[] __initdata = {
INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0),
INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),

2
arch/arm/mach-vexpress/ct-ca9x4.c
View File

@ -54,7 +54,9 @@ static struct map_desc ct_ca9x4_io_desc[] __initdata = {
static void __init ct_ca9x4_map_io(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = MMIO_P2V(A9_MPCORE_TWD);
#endif
v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}

2
arch/arm/mm/dma-mapping.c
View File

@ -198,7 +198,7 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
* fragmentation of the DMA space, and also prevents allocations
* smaller than a section from crossing a section boundary.
*/
bit = fls(size - 1) + 1;
bit = fls(size - 1);
if (bit > SECTION_SHIFT)
bit = SECTION_SHIFT;
align = 1 << bit;

4
arch/arm/plat-omap/devices.c
View File

@ -284,12 +284,14 @@ void __init omap_dsp_reserve_sdram_memblock(void)
if (!size)
return;
paddr = __memblock_alloc_base(size, SZ_1M, MEMBLOCK_REAL_LIMIT);
paddr = memblock_alloc(size, SZ_1M);
if (!paddr) {
pr_err("%s: failed to reserve %x bytes\n",
__func__, size);
return;
}
memblock_free(paddr, size);
memblock_remove(paddr, size);
omap_dsp_phys_mempool_base = paddr;
}

2
arch/arm/plat-omap/dma.c
View File

@ -1983,6 +1983,8 @@ static int omap2_dma_handle_ch(int ch)
dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
dma_write(1 << ch, IRQSTATUS_L0);
/* read back the register to flush the write */
dma_read(IRQSTATUS_L0);
/* If the ch is not chained then chain_id will be -1 */
if (dma_chan[ch].chain_id != -1) {

3
arch/arm/plat-orion/include/plat/pcie.h
View File

@ -11,12 +11,15 @@
#ifndef __PLAT_PCIE_H
#define __PLAT_PCIE_H
struct pci_bus;
u32 orion_pcie_dev_id(void __iomem *base);
u32 orion_pcie_rev(void __iomem *base);
int orion_pcie_link_up(void __iomem *base);
int orion_pcie_x4_mode(void __iomem *base);
int orion_pcie_get_local_bus_nr(void __iomem *base);
void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
void orion_pcie_reset(void __iomem *base);
void orion_pcie_setup(void __iomem *base,
struct mbus_dram_target_info *dram);
int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,

5
arch/arm/plat-orion/pcie.c
View File

@ -181,11 +181,6 @@ void __init orion_pcie_setup(void __iomem *base,
u16 cmd;
u32 mask;
/*
* soft reset PCIe unit
*/
orion_pcie_reset(base);
/*
* Point PCIe unit MBUS decode windows to DRAM space.
*/

2
arch/m68k/include/asm/irqflags.h
View File

@ -2,7 +2,9 @@
#define _M68K_IRQFLAGS_H
#include <linux/types.h>
#ifdef CONFIG_MMU
#include <linux/hardirq.h>
#endif
#include <linux/preempt.h>
#include <asm/thread_info.h>
#include <asm/entry.h>

1
arch/m68k/include/asm/machdep.h
View File

@ -40,5 +40,6 @@ extern unsigned long hw_timer_offset(void);
extern irqreturn_t arch_timer_interrupt(int irq, void *dummy);
extern void config_BSP(char *command, int len);
extern void do_IRQ(int irq, struct pt_regs *fp);
#endif /* _M68K_MACHDEP_H */

2
arch/powerpc/kernel/kvm.c
View File

@ -127,7 +127,7 @@ static void kvm_patch_ins_nop(u32 *inst)
static void kvm_patch_ins_b(u32 *inst, int addr)
{
#ifdef CONFIG_RELOCATABLE
#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_PPC_BOOK3S)
/* On relocatable kernels interrupts handlers and our code
can be in different regions, so we don't patch them */

2
arch/powerpc/kvm/booke_interrupts.S
View File

@ -416,7 +416,7 @@ lightweight_exit:
lwz r3, VCPU_PC(r4)
mtsrr0 r3
lwz r3, VCPU_SHARED(r4)
lwz r3, VCPU_SHARED_MSR(r3)
lwz r3, (VCPU_SHARED_MSR + 4)(r3)
oris r3, r3, KVMPPC_MSR_MASK@h
ori r3, r3, KVMPPC_MSR_MASK@l
mtsrr1 r3

2
arch/powerpc/kvm/e500.c
View File

@ -138,8 +138,8 @@ void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
free_page((unsigned long)vcpu->arch.shared);
kvmppc_e500_tlb_uninit(vcpu_e500);
kvm_vcpu_uninit(vcpu);
kvmppc_e500_tlb_uninit(vcpu_e500);
kmem_cache_free(kvm_vcpu_cache, vcpu_e500);
}

1
arch/powerpc/kvm/powerpc.c
View File

@ -617,6 +617,7 @@ long kvm_arch_vm_ioctl(struct file *filp,
switch (ioctl) {
case KVM_PPC_GET_PVINFO: {
struct kvm_ppc_pvinfo pvinfo;
memset(&pvinfo, 0, sizeof(pvinfo));
r = kvm_vm_ioctl_get_pvinfo(&pvinfo);
if (copy_to_user(argp, &pvinfo, sizeof(pvinfo))) {
r = -EFAULT;

2
arch/powerpc/kvm/timing.c
View File

@ -35,7 +35,6 @@ void kvmppc_init_timing_stats(struct kvm_vcpu *vcpu)
int i;
/* pause guest execution to avoid concurrent updates */
local_irq_disable();
mutex_lock(&vcpu->mutex);
vcpu->arch.last_exit_type = 0xDEAD;
@ -51,7 +50,6 @@ void kvmppc_init_timing_stats(struct kvm_vcpu *vcpu)
vcpu->arch.timing_last_enter.tv64 = 0;
mutex_unlock(&vcpu->mutex);
local_irq_enable();
}
static void add_exit_timing(struct kvm_vcpu *vcpu, u64 duration, int type)

1
arch/sh/Kconfig
View File

@ -193,6 +193,7 @@ config CPU_SH2
config CPU_SH2A
bool
select CPU_SH2
select UNCACHED_MAPPING
config CPU_SH3
bool

3
arch/sh/Makefile
View File

@ -133,10 +133,7 @@ machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se
machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx
machdir-$(CONFIG_SH_DREAMCAST) += mach-dreamcast
machdir-$(CONFIG_SH_SH03) += mach-sh03
machdir-$(CONFIG_SH_SECUREEDGE5410) += mach-snapgear
machdir-$(CONFIG_SH_RTS7751R2D) += mach-r2d
machdir-$(CONFIG_SH_7751_SYSTEMH) += mach-systemh
machdir-$(CONFIG_SH_EDOSK7705) += mach-edosk7705
machdir-$(CONFIG_SH_HIGHLANDER) += mach-highlander
machdir-$(CONFIG_SH_MIGOR) += mach-migor
machdir-$(CONFIG_SH_AP325RXA) += mach-ap325rxa

7
arch/sh/boards/Kconfig
View File

@ -81,13 +81,6 @@ config SH_7343_SOLUTION_ENGINE
Select 7343 SolutionEngine if configuring for a Hitachi
SH7343 (SH-Mobile 3AS) evaluation board.
config SH_7751_SYSTEMH
bool "SystemH7751R"
depends on CPU_SUBTYPE_SH7751R
help
Select SystemH if you are configuring for a Renesas SystemH
7751R evaluation board.
config SH_HP6XX
bool "HP6XX"
select SYS_SUPPORTS_APM_EMULATION

2
arch/sh/boards/Makefile
View File

@ -2,10 +2,12 @@
# Specific board support, not covered by a mach group.
#
obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
obj-$(CONFIG_SH_SECUREEDGE5410) += board-secureedge5410.o
obj-$(CONFIG_SH_SH2007) += board-sh2007.o
obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o
obj-$(CONFIG_SH_URQUELL) += board-urquell.o
obj-$(CONFIG_SH_SHMIN) += board-shmin.o
obj-$(CONFIG_SH_EDOSK7705) += board-edosk7705.o
obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o
obj-$(CONFIG_SH_ESPT) += board-espt.o
obj-$(CONFIG_SH_POLARIS) += board-polaris.o

78
arch/sh/boards/board-edosk7705.c Normal file
View File

@ -0,0 +1,78 @@
/*
* arch/sh/boards/renesas/edosk7705/setup.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Hitachi SolutionEngine Support.
*
* Modified for edosk7705 development
* board by S. Dunn, 2003.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/smc91x.h>
#include <asm/machvec.h>
#include <asm/sizes.h>
#define SMC_IOBASE 0xA2000000
#define SMC_IO_OFFSET 0x300
#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET)
#define ETHERNET_IRQ 0x09
static void __init sh_edosk7705_init_irq(void)
{
make_imask_irq(ETHERNET_IRQ);
}
/* eth initialization functions */
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL,
};
static struct resource smc91x_res[] = {
[0] = {
.start = SMC_IOADDR,
.end = SMC_IOADDR + SZ_32 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = ETHERNET_IRQ,
.end = ETHERNET_IRQ,
.flags = IORESOURCE_IRQ ,
}
};
static struct platform_device smc91x_dev = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(smc91x_res),
.resource = smc91x_res,
.dev = {
.platform_data = &smc91x_info,
},
};
/* platform init code */
static struct platform_device *edosk7705_devices[] __initdata = {
&smc91x_dev,
};
static int __init init_edosk7705_devices(void)
{
return platform_add_devices(edosk7705_devices,
ARRAY_SIZE(edosk7705_devices));
}
__initcall(init_edosk7705_devices);
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_edosk7705 __initmv = {
.mv_name = "EDOSK7705",
.mv_nr_irqs = 80,
.mv_init_irq = sh_edosk7705_init_irq,
};

38
arch/sh/boards/mach-snapgear/setup.c → arch/sh/boards/board-secureedge5410.c
View File

@ -1,6 +1,4 @@
/*
* linux/arch/sh/boards/snapgear/setup.c
*
* Copyright (C) 2002 David McCullough <davidm@snapgear.com>
* Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
*
@ -19,18 +17,19 @@
#include <linux/module.h>
#include <linux/sched.h>
#include <asm/machvec.h>
#include <mach/snapgear.h>
#include <mach/secureedge5410.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <cpu/timer.h>
unsigned short secureedge5410_ioport;
/*
* EraseConfig handling functions
*/
static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
{
(void)__raw_readb(0xb8000000); /* dummy read */
ctrl_delay(); /* dummy read */
printk("SnapGear: erase switch interrupt!\n");
@ -39,21 +38,22 @@ static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
static int __init eraseconfig_init(void)
{
unsigned int irq = evt2irq(0x240);
printk("SnapGear: EraseConfig init\n");
/* Setup "EraseConfig" switch on external IRQ 0 */
if (request_irq(IRL0_IRQ, eraseconfig_interrupt, IRQF_DISABLED,
if (request_irq(irq, eraseconfig_interrupt, IRQF_DISABLED,
"Erase Config", NULL))
printk("SnapGear: failed to register IRQ%d for Reset witch\n",
IRL0_IRQ);
irq);
else
printk("SnapGear: registered EraseConfig switch on IRQ%d\n",
IRL0_IRQ);
return(0);
irq);
return 0;
}
module_init(eraseconfig_init);
/****************************************************************************/
/*
* Initialize IRQ setting
*
@ -62,7 +62,6 @@ module_init(eraseconfig_init);
* IRL2 = eth1
* IRL3 = crypto
*/
static void __init init_snapgear_IRQ(void)
{
printk("Setup SnapGear IRQ/IPR ...\n");
@ -76,20 +75,5 @@ static void __init init_snapgear_IRQ(void)
static struct sh_machine_vector mv_snapgear __initmv = {
.mv_name = "SnapGear SecureEdge5410",
.mv_nr_irqs = 72,
.mv_inb = snapgear_inb,
.mv_inw = snapgear_inw,
.mv_inl = snapgear_inl,
.mv_outb = snapgear_outb,
.mv_outw = snapgear_outw,
.mv_outl = snapgear_outl,
.mv_inb_p = snapgear_inb_p,
.mv_inw_p = snapgear_inw,
.mv_inl_p = snapgear_inl,
.mv_outb_p = snapgear_outb_p,
.mv_outw_p = snapgear_outw,
.mv_outl_p = snapgear_outl,
.mv_init_irq = init_snapgear_IRQ,
};

5
arch/sh/boards/mach-edosk7705/Makefile
View File

@ -1,5 +0,0 @@
#
# Makefile for the EDOSK7705 specific parts of the kernel
#
obj-y := setup.o io.o

71
arch/sh/boards/mach-edosk7705/io.c
View File

@ -1,71 +0,0 @@
/*
* arch/sh/boards/renesas/edosk7705/io.c
*
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
* Based largely on io_se.c.
*
* I/O routines for Hitachi EDOSK7705 board.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/io.h>
#include <mach/edosk7705.h>
#include <asm/addrspace.h>
#define SMC_IOADDR 0xA2000000
/* Map the Ethernet addresses as if it is at 0x300 - 0x320 */
static unsigned long sh_edosk7705_isa_port2addr(unsigned long port)
{
/*
* SMC91C96 registers are 4 byte aligned rather than the
* usual 2 byte!
*/
if (port >= 0x300 && port < 0x320)
return SMC_IOADDR + ((port - 0x300) * 2);
maybebadio(port);
return port;
}
/* Trying to read / write bytes on odd-byte boundaries to the Ethernet
* registers causes problems. So we bit-shift the value and read / write
* in 2 byte chunks. Setting the low byte to 0 does not cause problems
* now as odd byte writes are only made on the bit mask / interrupt
* register. This may not be the case in future Mar-2003 SJD
*/
unsigned char sh_edosk7705_inb(unsigned long port)
{
if (port >= 0x300 && port < 0x320 && port & 0x01)
return __raw_readw(port - 1) >> 8;
return __raw_readb(sh_edosk7705_isa_port2addr(port));
}
void sh_edosk7705_outb(unsigned char value, unsigned long port)
{
if (port >= 0x300 && port < 0x320 && port & 0x01) {
__raw_writew(((unsigned short)value << 8), port - 1);
return;
}
__raw_writeb(value, sh_edosk7705_isa_port2addr(port));
}
void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count)
{
unsigned char *p = addr;
while (count--)
*p++ = sh_edosk7705_inb(port);
}
void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count)
{
unsigned char *p = (unsigned char *)addr;
while (count--)
sh_edosk7705_outb(*p++, port);
}

36
arch/sh/boards/mach-edosk7705/setup.c
View File

@ -1,36 +0,0 @@
/*
* arch/sh/boards/renesas/edosk7705/setup.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Hitachi SolutionEngine Support.
*
* Modified for edosk7705 development
* board by S. Dunn, 2003.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/machvec.h>
#include <mach/edosk7705.h>
static void __init sh_edosk7705_init_irq(void)
{
/* This is the Ethernet interrupt */
make_imask_irq(0x09);
}
/*
* The Machine Vector
*/
static struct sh_machine_vector mv_edosk7705 __initmv = {
.mv_name = "EDOSK7705",
.mv_nr_irqs = 80,
.mv_inb = sh_edosk7705_inb,
.mv_outb = sh_edosk7705_outb,
.mv_insb = sh_edosk7705_insb,
.mv_outsb = sh_edosk7705_outsb,
.mv_init_irq = sh_edosk7705_init_irq,
};

246
arch/sh/boards/mach-microdev/io.c
View File

@ -54,7 +54,7 @@
/*
* map I/O ports to memory-mapped addresses
*/
static unsigned long microdev_isa_port2addr(unsigned long offset)
void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len)
{
unsigned long result;
@ -72,16 +72,6 @@ static unsigned long microdev_isa_port2addr(unsigned long offset)
* Configuration Registers
*/
result = IO_SUPERIO_PHYS + (offset << 1);
#if 0
} else if (offset == KBD_DATA_REG || offset == KBD_CNTL_REG ||
offset == KBD_STATUS_REG) {
/*
* SMSC FDC37C93xAPM SuperIO chip
*
* PS/2 Keyboard + Mouse (ports 0x60 and 0x64).
*/
result = IO_SUPERIO_PHYS + (offset << 1);
#endif
} else if (((offset >= IO_IDE1_BASE) &&
(offset < IO_IDE1_BASE + IO_IDE_EXTENT)) ||
(offset == IO_IDE1_MISC)) {
@ -131,237 +121,5 @@ static unsigned long microdev_isa_port2addr(unsigned long offset)
result = PVR;
}
return result;
}
#define PORT2ADDR(x) (microdev_isa_port2addr(x))
static inline void delay(void)
{
#if defined(CONFIG_PCI)
/* System board present, just make a dummy SRAM access. (CS0 will be
mapped to PCI memory, probably good to avoid it.) */
__raw_readw(0xa6800000);
#else
/* CS0 will be mapped to flash, ROM etc so safe to access it. */
__raw_readw(0xa0000000);
#endif
}
unsigned char microdev_inb(unsigned long port)
{
#ifdef CONFIG_PCI
if (port >= PCIBIOS_MIN_IO)
return microdev_pci_inb(port);
#endif
return *(volatile unsigned char*)PORT2ADDR(port);
}
unsigned short microdev_inw(unsigned long port)
{
#ifdef CONFIG_PCI
if (port >= PCIBIOS_MIN_IO)
return microdev_pci_inw(port);
#endif
return *(volatile unsigned short*)PORT2ADDR(port);
}
unsigned int microdev_inl(unsigned long port)
{
#ifdef CONFIG_PCI
if (port >= PCIBIOS_MIN_IO)
return microdev_pci_inl(port);
#endif
return *(volatile unsigned int*)PORT2ADDR(port);
}
void microdev_outw(unsigned short b, unsigned long port)
{
#ifdef CONFIG_PCI
if (port >= PCIBIOS_MIN_IO) {
microdev_pci_outw(b, port);
return;
}
#endif
*(volatile unsigned short*)PORT2ADDR(port) = b;
}
void microdev_outb(unsigned char b, unsigned long port)
{
#ifdef CONFIG_PCI
if (port >= PCIBIOS_MIN_IO) {
microdev_pci_outb(b, port);
return;
}
#endif
/*
* There is a board feature with the current SH4-202 MicroDev in
* that the 2 byte enables (nBE0 and nBE1) are tied together (and
* to the Chip Select Line (Ethernet_CS)). Due to this connectivity,
* it is not possible to safely perform 8-bit writes to the
* Ethernet registers, as 16-bits will be consumed from the Data
* lines (corrupting the other byte). Hence, this function is
* written to implement 16-bit read/modify/write for all byte-wide
* accesses.
*
* Note: there is no problem with byte READS (even or odd).
*
* Sean McGoogan - 16th June 2003.
*/
if ((port >= IO_LAN91C111_BASE) &&
(port < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
/*
* Then are trying to perform a byte-write to the
* LAN91C111. This needs special care.
*/
if (port % 2 == 1) { /* is the port odd ? */
/* unset bit-0, i.e. make even */
const unsigned long evenPort = port-1;
unsigned short word;
/*
* do a 16-bit read/write to write to 'port',
* preserving even byte.
*
* Even addresses are bits 0-7
* Odd addresses are bits 8-15
*/
word = microdev_inw(evenPort);
word = (word & 0xffu) | (b << 8);
microdev_outw(word, evenPort);
} else {
/* else, we are trying to do an even byte write */
unsigned short word;
/*
* do a 16-bit read/write to write to 'port',
* preserving odd byte.
*
* Even addresses are bits 0-7
* Odd addresses are bits 8-15
*/
word = microdev_inw(port);
word = (word & 0xff00u) | (b);
microdev_outw(word, port);
}
} else {
*(volatile unsigned char*)PORT2ADDR(port) = b;
}
}
void microdev_outl(unsigned int b, unsigned long port)
{
#ifdef CONFIG_PCI
if (port >= PCIBIOS_MIN_IO) {
microdev_pci_outl(b, port);
return;
}
#endif
*(volatile unsigned int*)PORT2ADDR(port) = b;
}
unsigned char microdev_inb_p(unsigned long port)
{
unsigned char v = microdev_inb(port);
delay();
return v;
}
unsigned short microdev_inw_p(unsigned long port)
{
unsigned short v = microdev_inw(port);
delay();
return v;
}
unsigned int microdev_inl_p(unsigned long port)
{
unsigned int v = microdev_inl(port);
delay();
return v;
}
void microdev_outb_p(unsigned char b, unsigned long port)
{
microdev_outb(b, port);
delay();
}
void microdev_outw_p(unsigned short b, unsigned long port)
{
microdev_outw(b, port);
delay();
}
void microdev_outl_p(unsigned int b, unsigned long port)
{
microdev_outl(b, port);
delay();
}
void microdev_insb(unsigned long port, void *buffer, unsigned long count)
{
volatile unsigned char *port_addr;
unsigned char *buf = buffer;
port_addr = (volatile unsigned char *)PORT2ADDR(port);
while (count--)
*buf++ = *port_addr;
}
void microdev_insw(unsigned long port, void *buffer, unsigned long count)
{
volatile unsigned short *port_addr;
unsigned short *buf = buffer;
port_addr = (volatile unsigned short *)PORT2ADDR(port);
while (count--)
*buf++ = *port_addr;
}
void microdev_insl(unsigned long port, void *buffer, unsigned long count)
{
volatile unsigned long *port_addr;
unsigned int *buf = buffer;
port_addr = (volatile unsigned long *)PORT2ADDR(port);
while (count--)
*buf++ = *port_addr;
}
void microdev_outsb(unsigned long port, const void *buffer, unsigned long count)
{
volatile unsigned char *port_addr;
const unsigned char *buf = buffer;
port_addr = (volatile unsigned char *)PORT2ADDR(port);
while (count--)
*port_addr = *buf++;
}
void microdev_outsw(unsigned long port, const void *buffer, unsigned long count)
{
volatile unsigned short *port_addr;
const unsigned short *buf = buffer;
port_addr = (volatile unsigned short *)PORT2ADDR(port);
while (count--)
*port_addr = *buf++;
}
void microdev_outsl(unsigned long port, const void *buffer, unsigned long count)
{
volatile unsigned long *port_addr;
const unsigned int *buf = buffer;
port_addr = (volatile unsigned long *)PORT2ADDR(port);
while (count--)
*port_addr = *buf++;
return (void __iomem *)result;
}

23
arch/sh/boards/mach-microdev/setup.c
View File

@ -195,27 +195,6 @@ device_initcall(microdev_devices_setup);
static struct sh_machine_vector mv_sh4202_microdev __initmv = {
.mv_name = "SH4-202 MicroDev",
.mv_nr_irqs = 72,
.mv_inb = microdev_inb,
.mv_inw = microdev_inw,
.mv_inl = microdev_inl,
.mv_outb = microdev_outb,
.mv_outw = microdev_outw,
.mv_outl = microdev_outl,
.mv_inb_p = microdev_inb_p,
.mv_inw_p = microdev_inw_p,
.mv_inl_p = microdev_inl_p,
.mv_outb_p = microdev_outb_p,
.mv_outw_p = microdev_outw_p,
.mv_outl_p = microdev_outl_p,
.mv_insb = microdev_insb,
.mv_insw = microdev_insw,
.mv_insl = microdev_insl,
.mv_outsb = microdev_outsb,
.mv_outsw = microdev_outsw,
.mv_outsl = microdev_outsl,
.mv_ioport_map = microdev_ioport_map,
.mv_init_irq = init_microdev_irq,
};

2
arch/sh/boards/mach-se/7206/Makefile
View File

@ -2,4 +2,4 @@
# Makefile for the 7206 SolutionEngine specific parts of the kernel
#
obj-y := setup.o io.o irq.o
obj-y := setup.o irq.o

104
arch/sh/boards/mach-se/7206/io.c
View File

@ -1,104 +0,0 @@
/* $Id: io.c,v 1.5 2004/02/22 23:08:43 kkojima Exp $
*
* linux/arch/sh/boards/se/7206/io.c
*
* Copyright (C) 2006 Yoshinori Sato
*
* I/O routine for Hitachi 7206 SolutionEngine.
*
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/io.h>
#include <mach-se/mach/se7206.h>
static inline void delay(void)
{
__raw_readw(0x20000000); /* P2 ROM Area */
}
/* MS7750 requires special versions of in*, out* routines, since
PC-like io ports are located at upper half byte of 16-bit word which
can be accessed only with 16-bit wide. */
static inline volatile __u16 *
port2adr(unsigned int port)
{
if (port >= 0x2000 && port < 0x2020)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
else if (port >= 0x300 && port < 0x310)
return (volatile __u16 *) (PA_SMSC + (port - 0x300));
return (volatile __u16 *)port;
}
unsigned char se7206_inb(unsigned long port)
{
return (*port2adr(port)) & 0xff;
}
unsigned char se7206_inb_p(unsigned long port)
{
unsigned long v;
v = (*port2adr(port)) & 0xff;
delay();
return v;
}
unsigned short se7206_inw(unsigned long port)
{
return *port2adr(port);
}
void se7206_outb(unsigned char value, unsigned long port)
{
*(port2adr(port)) = value;
}
void se7206_outb_p(unsigned char value, unsigned long port)
{
*(port2adr(port)) = value;
delay();
}
void se7206_outw(unsigned short value, unsigned long port)
{
*port2adr(port) = value;
}
void se7206_insb(unsigned long port, void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
__u8 *ap = addr;
while (count--)
*ap++ = *p;
}
void se7206_insw(unsigned long port, void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
__u16 *ap = addr;
while (count--)
*ap++ = *p;
}
void se7206_outsb(unsigned long port, const void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
const __u8 *ap = addr;
while (count--)
*p = *ap++;
}
void se7206_outsw(unsigned long port, const void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
const __u16 *ap = addr;
while (count--)
*p = *ap++;
}

4
arch/sh/boards/mach-se/7206/irq.c
View File

@ -139,11 +139,13 @@ void __init init_se7206_IRQ(void)
make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
make_se7206_irq(IRQ1_IRQ); /* ATA */
make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
__raw_writew(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
__raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR); /* ICR1 */
/* FPGA System register setup*/
__raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
__raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
__raw_writew(0x0001,INTSEL);
}

15
arch/sh/boards/mach-se/7206/setup.c
View File

@ -86,20 +86,5 @@ __initcall(se7206_devices_setup);
static struct sh_machine_vector mv_se __initmv = {
.mv_name = "SolutionEngine",
.mv_nr_irqs = 256,
.mv_inb = se7206_inb,
.mv_inw = se7206_inw,
.mv_outb = se7206_outb,
.mv_outw = se7206_outw,
.mv_inb_p = se7206_inb_p,
.mv_inw_p = se7206_inw,
.mv_outb_p = se7206_outb_p,
.mv_outw_p = se7206_outw,
.mv_insb = se7206_insb,
.mv_insw = se7206_insw,
.mv_outsb = se7206_outsb,
.mv_outsw = se7206_outsw,
.mv_init_irq = init_se7206_IRQ,
};

2
arch/sh/boards/mach-se/770x/Makefile
View File

@ -2,4 +2,4 @@
# Makefile for the 770x SolutionEngine specific parts of the kernel
#
obj-y := setup.o io.o irq.o
obj-y := setup.o irq.o

156
arch/sh/boards/mach-se/770x/io.c
View File

@ -1,156 +0,0 @@
/*
* Copyright (C) 2000 Kazumoto Kojima
*
* I/O routine for Hitachi SolutionEngine.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/io.h>
#include <mach-se/mach/se.h>
/* MS7750 requires special versions of in*, out* routines, since
PC-like io ports are located at upper half byte of 16-bit word which
can be accessed only with 16-bit wide. */
static inline volatile __u16 *
port2adr(unsigned int port)
{
if (port & 0xff000000)
return ( volatile __u16 *) port;
if (port >= 0x2000)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
else if (port >= 0x1000)
return (volatile __u16 *) (PA_83902 + (port << 1));
else
return (volatile __u16 *) (PA_SUPERIO + (port << 1));
}
static inline int
shifted_port(unsigned long port)
{
/* For IDE registers, value is not shifted */
if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
return 0;
else
return 1;
}
unsigned char se_inb(unsigned long port)
{
if (shifted_port(port))
return (*port2adr(port) >> 8);
else
return (*port2adr(port))&0xff;
}
unsigned char se_inb_p(unsigned long port)
{
unsigned long v;
if (shifted_port(port))
v = (*port2adr(port) >> 8);
else
v = (*port2adr(port))&0xff;
ctrl_delay();
return v;
}
unsigned short se_inw(unsigned long port)
{
if (port >= 0x2000)
return *port2adr(port);
else
maybebadio(port);
return 0;
}
unsigned int se_inl(unsigned long port)
{
maybebadio(port);
return 0;
}
void se_outb(unsigned char value, unsigned long port)
{
if (shifted_port(port))
*(port2adr(port)) = value << 8;
else
*(port2adr(port)) = value;
}
void se_outb_p(unsigned char value, unsigned long port)
{
if (shifted_port(port))
*(port2adr(port)) = value << 8;
else
*(port2adr(port)) = value;
ctrl_delay();
}
void se_outw(unsigned short value, unsigned long port)
{
if (port >= 0x2000)
*port2adr(port) = value;
else
maybebadio(port);
}
void se_outl(unsigned int value, unsigned long port)
{
maybebadio(port);
}
void se_insb(unsigned long port, void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
__u8 *ap = addr;
if (shifted_port(port)) {
while (count--)
*ap++ = *p >> 8;
} else {
while (count--)
*ap++ = *p;
}
}
void se_insw(unsigned long port, void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
__u16 *ap = addr;
while (count--)
*ap++ = *p;
}
void se_insl(unsigned long port, void *addr, unsigned long count)
{
maybebadio(port);
}
void se_outsb(unsigned long port, const void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
const __u8 *ap = addr;
if (shifted_port(port)) {
while (count--)
*p = *ap++ << 8;
} else {
while (count--)
*p = *ap++;
}
}
void se_outsw(unsigned long port, const void *addr, unsigned long count)
{
volatile __u16 *p = port2adr(port);
const __u16 *ap = addr;
while (count--)
*p = *ap++;
}
void se_outsl(unsigned long port, const void *addr, unsigned long count)
{
maybebadio(port);
}

22
arch/sh/boards/mach-se/770x/setup.c
View File

@ -195,27 +195,5 @@ static struct sh_machine_vector mv_se __initmv = {
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
.mv_nr_irqs = 104,
#endif
.mv_inb = se_inb,
.mv_inw = se_inw,
.mv_inl = se_inl,
.mv_outb = se_outb,
.mv_outw = se_outw,
.mv_outl = se_outl,
.mv_inb_p = se_inb_p,
.mv_inw_p = se_inw,
.mv_inl_p = se_inl,
.mv_outb_p = se_outb_p,
.mv_outw_p = se_outw,
.mv_outl_p = se_outl,
.mv_insb = se_insb,
.mv_insw = se_insw,
.mv_insl = se_insl,
.mv_outsb = se_outsb,
.mv_outsw = se_outsw,
.mv_outsl = se_outsl,
.mv_init_irq = init_se_IRQ,
};

2
arch/sh/boards/mach-se/7751/Makefile
View File

@ -2,4 +2,4 @@
# Makefile for the 7751 SolutionEngine specific parts of the kernel
#
obj-y := setup.o io.o irq.o
obj-y := setup.o irq.o

119
arch/sh/boards/mach-se/7751/io.c
View File

@ -1,119 +0,0 @@
/*
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
* Based largely on io_se.c.
*
* I/O routine for Hitachi 7751 SolutionEngine.
*
* Initial version only to support LAN access; some
* placeholder code from io_se.c left in with the
* expectation of later SuperIO and PCMCIA access.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <mach-se/mach/se7751.h>
#include <asm/addrspace.h>
static inline volatile u16 *port2adr(unsigned int port)
{
if (port >= 0x2000)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
maybebadio((unsigned long)port);
return (volatile __u16*)port;
}
/*
* General outline: remap really low stuff [eventually] to SuperIO,
* stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
* is mapped through the PCI IO window. Stuff with high bits (PXSEG)
* should be way beyond the window, and is used w/o translation for
* compatibility.
*/
unsigned char sh7751se_inb(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned char *)port;
else
return (*port2adr(port)) & 0xff;
}
unsigned char sh7751se_inb_p(unsigned long port)
{
unsigned char v;
if (PXSEG(port))
v = *(volatile unsigned char *)port;
else
v = (*port2adr(port)) & 0xff;
ctrl_delay();
return v;
}
unsigned short sh7751se_inw(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned short *)port;
else if (port >= 0x2000)
return *port2adr(port);
else
maybebadio(port);
return 0;
}
unsigned int sh7751se_inl(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned long *)port;
else if (port >= 0x2000)
return *port2adr(port);
else
maybebadio(port);
return 0;
}
void sh7751se_outb(unsigned char value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else
*(port2adr(port)) = value;
}
void sh7751se_outb_p(unsigned char value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else
*(port2adr(port)) = value;
ctrl_delay();
}
void sh7751se_outw(unsigned short value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned short *)port = value;
else if (port >= 0x2000)
*port2adr(port) = value;
else
maybebadio(port);
}
void sh7751se_outl(unsigned int value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned long *)port = value;
else
maybebadio(port);
}
void sh7751se_insl(unsigned long port, void *addr, unsigned long count)
{
maybebadio(port);
}
void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count)
{
maybebadio(port);
}

18
arch/sh/boards/mach-se/7751/setup.c
View File

@ -56,23 +56,5 @@ __initcall(se7751_devices_setup);
static struct sh_machine_vector mv_7751se __initmv = {
.mv_name = "7751 SolutionEngine",
.mv_nr_irqs = 72,
.mv_inb = sh7751se_inb,
.mv_inw = sh7751se_inw,
.mv_inl = sh7751se_inl,
.mv_outb = sh7751se_outb,
.mv_outw = sh7751se_outw,
.mv_outl = sh7751se_outl,
.mv_inb_p = sh7751se_inb_p,
.mv_inw_p = sh7751se_inw,
.mv_inl_p = sh7751se_inl,
.mv_outb_p = sh7751se_outb_p,
.mv_outw_p = sh7751se_outw,
.mv_outl_p = sh7751se_outl,
.mv_insl = sh7751se_insl,
.mv_outsl = sh7751se_outsl,
.mv_init_irq = init_7751se_IRQ,
};

5
arch/sh/boards/mach-snapgear/Makefile
View File

@ -1,5 +0,0 @@
#
# Makefile for the SnapGear specific parts of the kernel
#
obj-y := setup.o io.o

121
arch/sh/boards/mach-snapgear/io.c
View File

@ -1,121 +0,0 @@
/*
* Copyright (C) 2002 David McCullough <davidm@snapgear.com>
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
* Based largely on io_se.c.
*
* I/O routine for Hitachi 7751 SolutionEngine.
*
* Initial version only to support LAN access; some
* placeholder code from io_se.c left in with the
* expectation of later SuperIO and PCMCIA access.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#ifdef CONFIG_SH_SECUREEDGE5410
unsigned short secureedge5410_ioport;
#endif
static inline volatile __u16 *port2adr(unsigned int port)
{
maybebadio((unsigned long)port);
return (volatile __u16*)port;
}
/*
* General outline: remap really low stuff [eventually] to SuperIO,
* stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
* is mapped through the PCI IO window. Stuff with high bits (PXSEG)
* should be way beyond the window, and is used w/o translation for
* compatibility.
*/
unsigned char snapgear_inb(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned char *)port;
else
return (*port2adr(port)) & 0xff;
}
unsigned char snapgear_inb_p(unsigned long port)
{
unsigned char v;
if (PXSEG(port))
v = *(volatile unsigned char *)port;
else
v = (*port2adr(port))&0xff;
ctrl_delay();
return v;
}
unsigned short snapgear_inw(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned short *)port;
else if (port >= 0x2000)
return *port2adr(port);
else
maybebadio(port);
return 0;
}
unsigned int snapgear_inl(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned long *)port;
else if (port >= 0x2000)
return *port2adr(port);
else
maybebadio(port);
return 0;
}
void snapgear_outb(unsigned char value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else
*(port2adr(port)) = value;
}
void snapgear_outb_p(unsigned char value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else
*(port2adr(port)) = value;
ctrl_delay();
}
void snapgear_outw(unsigned short value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned short *)port = value;
else if (port >= 0x2000)
*port2adr(port) = value;
else
maybebadio(port);
}
void snapgear_outl(unsigned int value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned long *)port = value;
else
maybebadio(port);
}
void snapgear_insl(unsigned long port, void *addr, unsigned long count)
{
maybebadio(port);
}
void snapgear_outsl(unsigned long port, const void *addr, unsigned long count)
{
maybebadio(port);
}

13
arch/sh/boards/mach-systemh/Makefile
View File

@ -1,13 +0,0 @@
#
# Makefile for the SystemH specific parts of the kernel
#
obj-y := setup.o irq.o io.o
# XXX: This wants to be consolidated in arch/sh/drivers/pci, and more
# importantly, with the generic sh7751_pcic_init() code. For now, we'll
# just abuse the hell out of kbuild, because we can..
obj-$(CONFIG_PCI) += pci.o
pci-y := ../../se/7751/pci.o

158
arch/sh/boards/mach-systemh/io.c
View File

@ -1,158 +0,0 @@
/*
* linux/arch/sh/boards/renesas/systemh/io.c
*
* Copyright (C) 2001 Ian da Silva, Jeremy Siegel
* Based largely on io_se.c.
*
* I/O routine for Hitachi 7751 Systemh.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <mach/systemh7751.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#define ETHER_IOMAP(adr) (0xB3000000 + (adr)) /*map to 16bits access area
of smc lan chip*/
static inline volatile __u16 *
port2adr(unsigned int port)
{
if (port >= 0x2000)
return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
maybebadio((unsigned long)port);
return (volatile __u16*)port;
}
/*
* General outline: remap really low stuff [eventually] to SuperIO,
* stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
* is mapped through the PCI IO window. Stuff with high bits (PXSEG)
* should be way beyond the window, and is used w/o translation for
* compatibility.
*/
unsigned char sh7751systemh_inb(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned char *)port;
else if (port <= 0x3F1)
return *(volatile unsigned char *)ETHER_IOMAP(port);
else
return (*port2adr(port))&0xff;
}
unsigned char sh7751systemh_inb_p(unsigned long port)
{
unsigned char v;
if (PXSEG(port))
v = *(volatile unsigned char *)port;
else if (port <= 0x3F1)
v = *(volatile unsigned char *)ETHER_IOMAP(port);
else
v = (*port2adr(port))&0xff;
ctrl_delay();
return v;
}
unsigned short sh7751systemh_inw(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned short *)port;
else if (port >= 0x2000)
return *port2adr(port);
else if (port <= 0x3F1)
return *(volatile unsigned int *)ETHER_IOMAP(port);
else
maybebadio(port);
return 0;
}
unsigned int sh7751systemh_inl(unsigned long port)
{
if (PXSEG(port))
return *(volatile unsigned long *)port;
else if (port >= 0x2000)
return *port2adr(port);
else if (port <= 0x3F1)
return *(volatile unsigned int *)ETHER_IOMAP(port);
else
maybebadio(port);
return 0;
}
void sh7751systemh_outb(unsigned char value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else if (port <= 0x3F1)
*(volatile unsigned char *)ETHER_IOMAP(port) = value;
else
*(port2adr(port)) = value;
}
void sh7751systemh_outb_p(unsigned char value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned char *)port = value;
else if (port <= 0x3F1)
*(volatile unsigned char *)ETHER_IOMAP(port) = value;
else
*(port2adr(port)) = value;
ctrl_delay();
}
void sh7751systemh_outw(unsigned short value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned short *)port = value;
else if (port >= 0x2000)
*port2adr(port) = value;
else if (port <= 0x3F1)
*(volatile unsigned short *)ETHER_IOMAP(port) = value;
else
maybebadio(port);
}
void sh7751systemh_outl(unsigned int value, unsigned long port)
{
if (PXSEG(port))
*(volatile unsigned long *)port = value;
else
maybebadio(port);
}
void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count)
{
unsigned char *p = addr;
while (count--) *p++ = sh7751systemh_inb(port);
}
void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count)
{
unsigned short *p = addr;
while (count--) *p++ = sh7751systemh_inw(port);
}
void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count)
{
maybebadio(port);
}
void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count)
{
unsigned char *p = (unsigned char*)addr;
while (count--) sh7751systemh_outb(*p++, port);
}
void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count)
{
unsigned short *p = (unsigned short*)addr;
while (count--) sh7751systemh_outw(*p++, port);
}
void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count)
{
maybebadio(port);
}

61
arch/sh/boards/mach-systemh/irq.c
View File

@ -1,61 +0,0 @@
/*
* linux/arch/sh/boards/renesas/systemh/irq.c
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Hitachi SystemH Support.
*
* Modified for 7751 SystemH by
* Jonathan Short.
*/
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/systemh7751.h>
#include <asm/smc37c93x.h>
/* address of external interrupt mask register
* address must be set prior to use these (maybe in init_XXX_irq())
* XXX : is it better to use .config than specifying it in code? */
static unsigned long *systemh_irq_mask_register = (unsigned long *)0xB3F10004;
static unsigned long *systemh_irq_request_register = (unsigned long *)0xB3F10000;
static void disable_systemh_irq(struct irq_data *data)
{
unsigned long val, mask = 0x01 << 1;
/* Clear the "irq"th bit in the mask and set it in the request */
val = __raw_readl((unsigned long)systemh_irq_mask_register);
val &= ~mask;
__raw_writel(val, (unsigned long)systemh_irq_mask_register);
val = __raw_readl((unsigned long)systemh_irq_request_register);
val |= mask;
__raw_writel(val, (unsigned long)systemh_irq_request_register);
}
static void enable_systemh_irq(struct irq_data *data)
{
unsigned long val, mask = 0x01 << 1;
/* Set "irq"th bit in the mask register */
val = __raw_readl((unsigned long)systemh_irq_mask_register);
val |= mask;
__raw_writel(val, (unsigned long)systemh_irq_mask_register);
}
static struct irq_chip systemh_irq_type = {
.name = "SystemH Register",
.irq_unmask = enable_systemh_irq,
.irq_mask = disable_systemh_irq,
};
void make_systemh_irq(unsigned int irq)
{
disable_irq_nosync(irq);
set_irq_chip_and_handler(irq, &systemh_irq_type, handle_level_irq);
disable_systemh_irq(irq_get_irq_data(irq));
}

57
arch/sh/boards/mach-systemh/setup.c
View File

@ -1,57 +0,0 @@
/*
* linux/arch/sh/boards/renesas/systemh/setup.c
*
* Copyright (C) 2000 Kazumoto Kojima
* Copyright (C) 2003 Paul Mundt
*
* Hitachi SystemH Support.
*
* Modified for 7751 SystemH by Jonathan Short.
*
* Rewritten for 2.6 by Paul Mundt.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <asm/machvec.h>
#include <mach/systemh7751.h>
extern void make_systemh_irq(unsigned int irq);
/*
* Initialize IRQ setting
*/
static void __init sh7751systemh_init_irq(void)
{
make_systemh_irq(0xb); /* Ethernet interrupt */
}
static struct sh_machine_vector mv_7751systemh __initmv = {
.mv_name = "7751 SystemH",
.mv_nr_irqs = 72,
.mv_inb = sh7751systemh_inb,
.mv_inw = sh7751systemh_inw,
.mv_inl = sh7751systemh_inl,
.mv_outb = sh7751systemh_outb,
.mv_outw = sh7751systemh_outw,
.mv_outl = sh7751systemh_outl,
.mv_inb_p = sh7751systemh_inb_p,
.mv_inw_p = sh7751systemh_inw,
.mv_inl_p = sh7751systemh_inl,
.mv_outb_p = sh7751systemh_outb_p,
.mv_outw_p = sh7751systemh_outw,
.mv_outl_p = sh7751systemh_outl,
.mv_insb = sh7751systemh_insb,
.mv_insw = sh7751systemh_insw,
.mv_insl = sh7751systemh_insl,
.mv_outsb = sh7751systemh_outsb,
.mv_outsw = sh7751systemh_outsw,
.mv_outsl = sh7751systemh_outsl,
.mv_init_irq = sh7751systemh_init_irq,
};

0
arch/sh/configs/snapgear_defconfig → arch/sh/configs/secureedge5410_defconfig
View File

28
arch/sh/configs/systemh_defconfig
View File

@ -1,28 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_SYSCTL_SYSCALL is not set
# CONFIG_HOTPLUG is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_CPU_SUBTYPE_SH7751R=y
CONFIG_MEMORY_START=0x0c000000
CONFIG_MEMORY_SIZE=0x00400000
CONFIG_FLATMEM_MANUAL=y
CONFIG_SH_7751_SYSTEMH=y
CONFIG_PREEMPT=y
# CONFIG_STANDALONE is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=1024
# CONFIG_INPUT is not set
# CONFIG_SERIO_SERPORT is not set
# CONFIG_VT is not set
CONFIG_HW_RANDOM=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set

8
arch/sh/include/asm/addrspace.h
View File

@ -44,10 +44,10 @@
/*
* These will never work in 32-bit, don't even bother.
*/
#define P1SEGADDR(a) __futile_remapping_attempt
#define P2SEGADDR(a) __futile_remapping_attempt
#define P3SEGADDR(a) __futile_remapping_attempt
#define P4SEGADDR(a) __futile_remapping_attempt
#define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; })
#define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; })
#define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; })
#define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; })
#endif
#endif /* P1SEG */

12
arch/sh/include/asm/pgtable.h
View File

@ -66,7 +66,6 @@ static inline unsigned long long neff_sign_extend(unsigned long val)
#define PHYS_ADDR_MASK29 0x1fffffff
#define PHYS_ADDR_MASK32 0xffffffff
#ifdef CONFIG_PMB
static inline unsigned long phys_addr_mask(void)
{
/* Is the MMU in 29bit mode? */
@ -75,17 +74,6 @@ static inline unsigned long phys_addr_mask(void)
return PHYS_ADDR_MASK32;
}
#elif defined(CONFIG_32BIT)
static inline unsigned long phys_addr_mask(void)
{
return PHYS_ADDR_MASK32;
}
#else
static inline unsigned long phys_addr_mask(void)
{
return PHYS_ADDR_MASK29;
}
#endif
#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)

4
arch/sh/include/asm/system.h
View File

@ -10,6 +10,7 @@
#include <linux/compiler.h>
#include <linux/linkage.h>
#include <asm/types.h>
#include <asm/uncached.h>
#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
@ -137,9 +138,6 @@ extern unsigned int instruction_size(unsigned int insn);
#define instruction_size(insn) (4)
#endif
extern unsigned long cached_to_uncached;
extern unsigned long uncached_size;
void per_cpu_trap_init(void);
void default_idle(void);
void cpu_idle_wait(void);

36
arch/sh/include/asm/system_32.h
View File

@ -145,42 +145,6 @@ do { \
__restore_dsp(prev); \
} while (0)
/*
* Jump to uncached area.
* When handling TLB or caches, we need to do it from an uncached area.
*/
#define jump_to_uncached() \
do { \
unsigned long __dummy; \
\
__asm__ __volatile__( \
"mova 1f, %0\n\t" \
"add %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1:" \
: "=&z" (__dummy) \
: "r" (cached_to_uncached)); \
} while (0)
/*
* Back to cached area.
*/
#define back_to_cached() \
do { \
unsigned long __dummy; \
ctrl_barrier(); \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
#ifdef CONFIG_CPU_HAS_SR_RB
#define lookup_exception_vector() \
({ \

3
arch/sh/include/asm/system_64.h
View File

@ -34,9 +34,6 @@ do { \
&next->thread); \
} while (0)
#define jump_to_uncached() do { } while (0)
#define back_to_cached() do { } while (0)
#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))

40
arch/sh/include/asm/uncached.h
View File

@ -4,15 +4,55 @@
#include <linux/bug.h>
#ifdef CONFIG_UNCACHED_MAPPING
extern unsigned long cached_to_uncached;
extern unsigned long uncached_size;
extern unsigned long uncached_start, uncached_end;
extern int virt_addr_uncached(unsigned long kaddr);
extern void uncached_init(void);
extern void uncached_resize(unsigned long size);
/*
* Jump to uncached area.
* When handling TLB or caches, we need to do it from an uncached area.
*/
#define jump_to_uncached() \
do { \
unsigned long __dummy; \
\
__asm__ __volatile__( \
"mova 1f, %0\n\t" \
"add %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1:" \
: "=&z" (__dummy) \
: "r" (cached_to_uncached)); \
} while (0)
/*
* Back to cached area.
*/
#define back_to_cached() \
do { \
unsigned long __dummy; \
ctrl_barrier(); \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
#else
#define virt_addr_uncached(kaddr) (0)
#define uncached_init() do { } while (0)
#define uncached_resize(size) BUG()
#define jump_to_uncached() do { } while (0)
#define back_to_cached() do { } while (0)
#endif
#endif /* __ASM_SH_UNCACHED_H */

7
arch/sh/include/mach-common/mach/edosk7705.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_SH_EDOSK7705_H
#define __ASM_SH_EDOSK7705_H
#define __IO_PREFIX sh_edosk7705
#include <asm/io_generic.h>
#endif /* __ASM_SH_EDOSK7705_H */

9
arch/sh/include/mach-common/mach/microdev.h
View File

@ -68,13 +68,4 @@ extern void microdev_print_fpga_intc_status(void);
#define __IO_PREFIX microdev
#include <asm/io_generic.h>
#if defined(CONFIG_PCI)
unsigned char microdev_pci_inb(unsigned long port);
unsigned short microdev_pci_inw(unsigned long port);
unsigned long microdev_pci_inl(unsigned long port);
void microdev_pci_outb(unsigned char data, unsigned long port);
void microdev_pci_outw(unsigned short data, unsigned long port);
void microdev_pci_outl(unsigned long data, unsigned long port);
#endif
#endif /* __ASM_SH_MICRODEV_H */

22
arch/sh/include/mach-common/mach/snapgear.h → arch/sh/include/mach-common/mach/secureedge5410.h
View File

@ -12,30 +12,9 @@
#ifndef _ASM_SH_IO_SNAPGEAR_H
#define _ASM_SH_IO_SNAPGEAR_H
#if defined(CONFIG_CPU_SH4)
/*
* The external interrupt lines, these take up ints 0 - 15 inclusive
* depending on the priority for the interrupt. In fact the priority
* is the interrupt :-)
*/
#define IRL0_IRQ 2
#define IRL0_PRIORITY 13
#define IRL1_IRQ 5
#define IRL1_PRIORITY 10
#define IRL2_IRQ 8
#define IRL2_PRIORITY 7
#define IRL3_IRQ 11
#define IRL3_PRIORITY 4
#endif
#define __IO_PREFIX snapgear
#include <asm/io_generic.h>
#ifdef CONFIG_SH_SECUREEDGE5410
/*
* We need to remember what was written to the ioport as some bits
* are shared with other functions and you cannot read back what was
@ -66,6 +45,5 @@ extern unsigned short secureedge5410_ioport;
((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
#define SECUREEDGE_READ_IOPORT() \
((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
#endif
#endif /* _ASM_SH_IO_SNAPGEAR_H */

71
arch/sh/include/mach-common/mach/systemh7751.h
View File

@ -1,71 +0,0 @@
#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
/*
* linux/include/asm-sh/systemh/7751systemh.h
*
* Copyright (C) 2000 Kazumoto Kojima
*
* Hitachi SystemH support
* Modified for 7751 SystemH by
* Jonathan Short, 2002.
*/
/* Box specific addresses. */
#define PA_ROM 0x00000000 /* EPROM */
#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
#define PA_FROM 0x01000000 /* EPROM */
#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
#define PA_EXT1 0x04000000
#define PA_EXT1_SIZE 0x04000000
#define PA_EXT2 0x08000000
#define PA_EXT2_SIZE 0x04000000
#define PA_SDRAM 0x0c000000
#define PA_SDRAM_SIZE 0x04000000
#define PA_EXT4 0x12000000
#define PA_EXT4_SIZE 0x02000000
#define PA_EXT5 0x14000000
#define PA_EXT5_SIZE 0x04000000
#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */
#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */
#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */
#define PA_LED 0xba000000 /* LED */
#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */
#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */
#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */
#define MRSHPC_MODE (PA_MRSHPC + 4)
#define MRSHPC_OPTION (PA_MRSHPC + 6)
#define MRSHPC_CSR (PA_MRSHPC + 8)
#define MRSHPC_ISR (PA_MRSHPC + 10)
#define MRSHPC_ICR (PA_MRSHPC + 12)
#define MRSHPC_CPWCR (PA_MRSHPC + 14)
#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
#define MRSHPC_CDCR (PA_MRSHPC + 28)
#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
#define BCR_ILCRA (PA_BCR + 0)
#define BCR_ILCRB (PA_BCR + 2)
#define BCR_ILCRC (PA_BCR + 4)
#define BCR_ILCRD (PA_BCR + 6)
#define BCR_ILCRE (PA_BCR + 8)
#define BCR_ILCRF (PA_BCR + 10)
#define BCR_ILCRG (PA_BCR + 12)
#define IRQ_79C973 13
#define __IO_PREFIX sh7751systemh
#include <asm/io_generic.h>
#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */

6
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
View File

@ -48,7 +48,7 @@ static struct clk r_clk = {
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
struct clk extal_clk = {
static struct clk extal_clk = {
.rate = 33333333,
};
@ -111,7 +111,7 @@ static struct clk div3_clk = {
.parent = &pll_clk,
};
struct clk *main_clks[] = {
static struct clk *main_clks[] = {
&r_clk,
&extal_clk,
&fll_clk,
@ -156,7 +156,7 @@ struct clk div4_clks[DIV4_NR] = {
enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
struct clk div6_clks[DIV6_NR] = {
static struct clk div6_clks[DIV6_NR] = {
[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
[DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
[DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),

Some files were not shown because too many files have changed in this diff Show More