Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev: [PATCH] ata_piix: allow 01b MAP for both ICH6M and ICH7M [PATCH] libata: unexport ata_dev_revalidate() [PATCH] Add 0x7110 piix to ata_piix.c [PATCH] sata_sis: fix flags handling for the secondary port
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commit
30574b6161
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@ -126,8 +126,7 @@ enum {
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ich6_sata = 7,
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ich6_sata_ahci = 8,
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ich6m_sata_ahci = 9,
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ich7m_sata_ahci = 10,
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ich8_sata_ahci = 11,
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ich8_sata_ahci = 10,
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/* constants for mapping table */
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P0 = 0, /* port 0 */
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@ -169,6 +168,7 @@ static const struct pci_device_id piix_pci_tbl[] = {
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#ifdef ATA_ENABLE_PATA
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/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
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/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
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{ 0x8086, 0x7110, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
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{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
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{ 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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{ 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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@ -227,7 +227,7 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* 82801GB/GR/GH (ICH7, identical to ICH6) */
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{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci },
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
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/* Enterprise Southbridge 2 (where's the datasheet?) */
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{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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/* SATA Controller 1 IDE (ICH8, no datasheet yet) */
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@ -399,23 +399,10 @@ static const struct piix_map_db ich6m_map_db = {
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.mask = 0x3,
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.port_enable = 0x5,
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.present_shift = 4,
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.map = {
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/* PM PS SM SS MAP */
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{ P0, P2, RV, RV }, /* 00b */
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{ RV, RV, RV, RV },
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{ P0, P2, IDE, IDE }, /* 10b */
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{ RV, RV, RV, RV },
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},
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};
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static const struct piix_map_db ich7m_map_db = {
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.mask = 0x3,
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.port_enable = 0x5,
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.present_shift = 4,
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/* Map 01b isn't specified in the doc but some notebooks use
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* it anyway. ATM, the only case spotted carries subsystem ID
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* 1025:0107. This is the only difference from ich6m.
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* it anyway. MAP 01b have been spotted on both ICH6M and
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* ICH7M.
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*/
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.map = {
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/* PM PS SM SS MAP */
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@ -445,7 +432,6 @@ static const struct piix_map_db *piix_map_db_table[] = {
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[ich6_sata] = &ich6_map_db,
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[ich6_sata_ahci] = &ich6_map_db,
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[ich6m_sata_ahci] = &ich6m_map_db,
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[ich7m_sata_ahci] = &ich7m_map_db,
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[ich8_sata_ahci] = &ich8_map_db,
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};
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@ -556,19 +542,7 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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},
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/* ich7m_sata_ahci: 10 */
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{
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.sht = &piix_sht,
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.flags = ATA_FLAG_SATA |
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PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
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PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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/* ich8_sata_ahci: 11 */
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/* ich8_sata_ahci: 10 */
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{
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.sht = &piix_sht,
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.flags = ATA_FLAG_SATA |
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@ -6122,7 +6122,6 @@ EXPORT_SYMBOL_GPL(ata_std_prereset);
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EXPORT_SYMBOL_GPL(ata_std_softreset);
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EXPORT_SYMBOL_GPL(sata_std_hardreset);
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EXPORT_SYMBOL_GPL(ata_std_postreset);
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EXPORT_SYMBOL_GPL(ata_dev_revalidate);
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EXPORT_SYMBOL_GPL(ata_dev_classify);
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EXPORT_SYMBOL_GPL(ata_dev_pair);
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EXPORT_SYMBOL_GPL(ata_port_disable);
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@ -53,6 +53,7 @@ extern unsigned ata_exec_internal(struct ata_device *dev,
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extern unsigned int ata_do_simple_cmd(struct ata_device *dev, u8 cmd);
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extern int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
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int post_reset, u16 *id);
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extern int ata_dev_revalidate(struct ata_device *dev, int post_reset);
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extern int ata_dev_configure(struct ata_device *dev, int print_info);
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extern int sata_down_spd_limit(struct ata_port *ap);
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extern int sata_set_spd_needed(struct ata_port *ap);
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@ -240,7 +240,7 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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struct ata_probe_ent *probe_ent = NULL;
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int rc;
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u32 genctl;
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struct ata_port_info *ppi[2];
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struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi };
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int pci_dev_busy = 0;
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u8 pmr;
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u8 port2_start;
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@ -265,27 +265,20 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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if (rc)
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goto err_out_regions;
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ppi[0] = ppi[1] = &sis_port_info;
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probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
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if (!probe_ent) {
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rc = -ENOMEM;
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goto err_out_regions;
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}
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/* check and see if the SCRs are in IO space or PCI cfg space */
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pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
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if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
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probe_ent->port_flags |= SIS_FLAG_CFGSCR;
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pi.flags |= SIS_FLAG_CFGSCR;
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/* if hardware thinks SCRs are in IO space, but there are
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* no IO resources assigned, change to PCI cfg space.
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*/
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if ((!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) &&
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if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
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((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
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(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
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genctl &= ~GENCTL_IOMAPPED_SCR;
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pci_write_config_dword(pdev, SIS_GENCTL, genctl);
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probe_ent->port_flags |= SIS_FLAG_CFGSCR;
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pi.flags |= SIS_FLAG_CFGSCR;
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}
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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@ -306,6 +299,12 @@ static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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port2_start = 0x20;
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}
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probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
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if (!probe_ent) {
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rc = -ENOMEM;
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goto err_out_regions;
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}
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if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) {
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probe_ent->port[0].scr_addr =
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pci_resource_start(pdev, SIS_SCR_PCI_BAR);
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@ -702,7 +702,6 @@ extern int ata_std_prereset(struct ata_port *ap);
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extern int ata_std_softreset(struct ata_port *ap, unsigned int *classes);
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extern int sata_std_hardreset(struct ata_port *ap, unsigned int *class);
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extern void ata_std_postreset(struct ata_port *ap, unsigned int *classes);
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extern int ata_dev_revalidate(struct ata_device *dev, int post_reset);
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extern void ata_port_disable(struct ata_port *);
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extern void ata_std_ports(struct ata_ioports *ioaddr);
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#ifdef CONFIG_PCI
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