mtd: rawnand: gpmi: move all driver code into single file
This moves the whole driver into a single C file. The filename gpmi-lib implies that it implements library functions, but in fact there are several cases where functions in gpmi-lib.c call back into functions in gpmi-nand.c. With this one has to constantly jump between those two files, so moving it into a single file improves readability, even when the file gets quite large. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Sascha Hauer
Miquel Raynal
parent
bf82832228
commit
3045f8e369
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@ -1,4 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi_nand.o
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gpmi_nand-objs += gpmi-nand.o
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gpmi_nand-objs += gpmi-lib.o
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@ -1,934 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale GPMI NAND Flash Driver
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*
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* Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 Embedded Alley Solutions, Inc.
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*/
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include "gpmi-nand.h"
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#include "gpmi-regs.h"
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#include "bch-regs.h"
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/* Converts time to clock cycles */
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#define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
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#define MXS_SET_ADDR 0x4
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#define MXS_CLR_ADDR 0x8
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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* (bit 30).
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*/
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static int clear_poll_bit(void __iomem *addr, u32 mask)
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{
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int timeout = 0x400;
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/* clear the bit */
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writel(mask, addr + MXS_CLR_ADDR);
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/*
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* SFTRST needs 3 GPMI clocks to settle, the reference manual
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* recommends to wait 1us.
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*/
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udelay(1);
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/* poll the bit becoming clear */
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while ((readl(addr) & mask) && --timeout)
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/* nothing */;
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return !timeout;
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}
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#define MODULE_CLKGATE (1 << 30)
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#define MODULE_SFTRST (1 << 31)
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/*
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* The current mxs_reset_block() will do two things:
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* [1] enable the module.
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* [2] reset the module.
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*
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* In most of the cases, it's ok.
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* But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
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* If you try to soft reset the BCH block, it becomes unusable until
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* the next hard reset. This case occurs in the NAND boot mode. When the board
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* boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
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* So If the driver tries to reset the BCH again, the BCH will not work anymore.
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* You will see a DMA timeout in this case. The bug has been fixed
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* in the following chips, such as MX28.
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*
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* To avoid this bug, just add a new parameter `just_enable` for
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* the mxs_reset_block(), and rewrite it here.
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*/
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static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
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{
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int ret;
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int timeout = 0x400;
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear CLKGATE */
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writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
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if (!just_enable) {
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/* set SFTRST to reset the block */
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writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
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udelay(1);
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/* poll CLKGATE becoming set */
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while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
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/* nothing */;
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if (unlikely(!timeout))
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goto error;
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}
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear and poll CLKGATE */
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ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
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if (unlikely(ret))
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goto error;
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return 0;
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error:
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pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
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return -ETIMEDOUT;
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}
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static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
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{
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struct clk *clk;
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int ret;
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int i;
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for (i = 0; i < GPMI_CLK_MAX; i++) {
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clk = this->resources.clock[i];
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if (!clk)
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break;
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if (v) {
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ret = clk_prepare_enable(clk);
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if (ret)
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goto err_clk;
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} else {
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clk_disable_unprepare(clk);
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}
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}
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return 0;
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err_clk:
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for (; i > 0; i--)
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clk_disable_unprepare(this->resources.clock[i - 1]);
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return ret;
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}
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int gpmi_enable_clk(struct gpmi_nand_data *this)
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{
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return __gpmi_enable_clk(this, true);
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}
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int gpmi_disable_clk(struct gpmi_nand_data *this)
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{
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return __gpmi_enable_clk(this, false);
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}
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int gpmi_init(struct gpmi_nand_data *this)
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{
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struct resources *r = &this->resources;
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int ret;
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ret = gpmi_enable_clk(this);
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if (ret)
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return ret;
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ret = gpmi_reset_block(r->gpmi_regs, false);
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if (ret)
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goto err_out;
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/*
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* Reset BCH here, too. We got failures otherwise :(
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* See later BCH reset for explanation of MX23 and MX28 handling
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*/
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ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this));
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if (ret)
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goto err_out;
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/* Choose NAND mode. */
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writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
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/* Set the IRQ polarity. */
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writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
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r->gpmi_regs + HW_GPMI_CTRL1_SET);
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/* Disable Write-Protection. */
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writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
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/* Select BCH ECC. */
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writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
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/*
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* Decouple the chip select from dma channel. We use dma0 for all
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* the chips.
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*/
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writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
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gpmi_disable_clk(this);
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return 0;
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err_out:
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gpmi_disable_clk(this);
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return ret;
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}
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/* This function is very useful. It is called only when the bug occur. */
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void gpmi_dump_info(struct gpmi_nand_data *this)
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{
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struct resources *r = &this->resources;
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struct bch_geometry *geo = &this->bch_geometry;
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u32 reg;
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int i;
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dev_err(this->dev, "Show GPMI registers :\n");
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for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
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reg = readl(r->gpmi_regs + i * 0x10);
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dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
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}
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/* start to print out the BCH info */
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dev_err(this->dev, "Show BCH registers :\n");
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for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) {
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reg = readl(r->bch_regs + i * 0x10);
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dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
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}
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dev_err(this->dev, "BCH Geometry :\n"
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"GF length : %u\n"
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"ECC Strength : %u\n"
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"Page Size in Bytes : %u\n"
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"Metadata Size in Bytes : %u\n"
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"ECC Chunk Size in Bytes: %u\n"
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"ECC Chunk Count : %u\n"
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"Payload Size in Bytes : %u\n"
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"Auxiliary Size in Bytes: %u\n"
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"Auxiliary Status Offset: %u\n"
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"Block Mark Byte Offset : %u\n"
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"Block Mark Bit Offset : %u\n",
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geo->gf_len,
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geo->ecc_strength,
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geo->page_size,
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geo->metadata_size,
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geo->ecc_chunk_size,
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geo->ecc_chunk_count,
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geo->payload_size,
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geo->auxiliary_size,
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geo->auxiliary_status_offset,
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geo->block_mark_byte_offset,
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geo->block_mark_bit_offset);
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}
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/* Configures the geometry for BCH. */
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int bch_set_geometry(struct gpmi_nand_data *this)
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{
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struct resources *r = &this->resources;
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struct bch_geometry *bch_geo = &this->bch_geometry;
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unsigned int block_count;
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unsigned int block_size;
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unsigned int metadata_size;
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unsigned int ecc_strength;
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unsigned int page_size;
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unsigned int gf_len;
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int ret;
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ret = common_nfc_set_geometry(this);
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if (ret)
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return ret;
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block_count = bch_geo->ecc_chunk_count - 1;
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block_size = bch_geo->ecc_chunk_size;
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metadata_size = bch_geo->metadata_size;
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ecc_strength = bch_geo->ecc_strength >> 1;
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page_size = bch_geo->page_size;
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gf_len = bch_geo->gf_len;
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ret = gpmi_enable_clk(this);
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if (ret)
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return ret;
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/*
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* Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
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* chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
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* and MX28.
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*/
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ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this));
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if (ret)
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goto err_out;
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/* Configure layout 0. */
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writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
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| BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
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| BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
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| BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
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| BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
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r->bch_regs + HW_BCH_FLASH0LAYOUT0);
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writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
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| BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
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| BF_BCH_FLASH0LAYOUT1_GF(gf_len, this)
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| BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
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r->bch_regs + HW_BCH_FLASH0LAYOUT1);
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/* Set *all* chip selects to use layout 0. */
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writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
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/* Enable interrupts. */
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writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
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r->bch_regs + HW_BCH_CTRL_SET);
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gpmi_disable_clk(this);
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return 0;
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err_out:
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gpmi_disable_clk(this);
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return ret;
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}
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/*
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* <1> Firstly, we should know what's the GPMI-clock means.
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* The GPMI-clock is the internal clock in the gpmi nand controller.
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* If you set 100MHz to gpmi nand controller, the GPMI-clock's period
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* is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
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*
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* <2> Secondly, we should know what's the frequency on the nand chip pins.
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* The frequency on the nand chip pins is derived from the GPMI-clock.
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* We can get it from the following equation:
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*
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* F = G / (DS + DH)
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*
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* F : the frequency on the nand chip pins.
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* G : the GPMI clock, such as 100MHz.
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* DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
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* DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
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*
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* <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
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* the nand EDO(extended Data Out) timing could be applied.
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* The GPMI implements a feedback read strobe to sample the read data.
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* The feedback read strobe can be delayed to support the nand EDO timing
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* where the read strobe may deasserts before the read data is valid, and
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* read data is valid for some time after read strobe.
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*
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* The following figure illustrates some aspects of a NAND Flash read:
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*
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* |<---tREA---->|
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* | |
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* | | |
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* |<--tRP-->| |
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* | | |
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* __ ___|__________________________________
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* RDN \________/ |
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* |
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* /---------\
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* Read Data --------------< >---------
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* \---------/
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* | |
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* |<-D->|
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* FeedbackRDN ________ ____________
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* \___________/
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*
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* D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
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*
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*
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* <4> Now, we begin to describe how to compute the right RDN_DELAY.
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*
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* 4.1) From the aspect of the nand chip pins:
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* Delay = (tREA + C - tRP) {1}
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*
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* tREA : the maximum read access time.
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* C : a constant to adjust the delay. default is 4000ps.
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* tRP : the read pulse width, which is exactly:
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* tRP = (GPMI-clock-period) * DATA_SETUP
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*
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* 4.2) From the aspect of the GPMI nand controller:
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* Delay = RDN_DELAY * 0.125 * RP {2}
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*
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* RP : the DLL reference period.
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* if (GPMI-clock-period > DLL_THRETHOLD)
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* RP = GPMI-clock-period / 2;
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* else
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* RP = GPMI-clock-period;
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*
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* Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
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* is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
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* is 16000ps, but in mx6q, we use 12000ps.
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*
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* 4.3) since {1} equals {2}, we get:
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*
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* (tREA + 4000 - tRP) * 8
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* RDN_DELAY = ----------------------- {3}
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* RP
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*/
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static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
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const struct nand_sdr_timings *sdr)
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{
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struct gpmi_nfc_hardware_timing *hw = &this->hw;
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unsigned int dll_threshold_ps = this->devdata->max_chain_delay;
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unsigned int period_ps, reference_period_ps;
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unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles;
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unsigned int tRP_ps;
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bool use_half_period;
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int sample_delay_ps, sample_delay_factor;
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u16 busy_timeout_cycles;
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u8 wrn_dly_sel;
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if (sdr->tRC_min >= 30000) {
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/* ONFI non-EDO modes [0-3] */
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hw->clk_rate = 22000000;
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wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
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} else if (sdr->tRC_min >= 25000) {
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/* ONFI EDO mode 4 */
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hw->clk_rate = 80000000;
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wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
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} else {
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/* ONFI EDO mode 5 */
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hw->clk_rate = 100000000;
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wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
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}
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/* SDR core timings are given in picoseconds */
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period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate);
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addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps);
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data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps);
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data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps);
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busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps);
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hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) |
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BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles) |
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BF_GPMI_TIMING0_DATA_SETUP(data_setup_cycles);
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hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(busy_timeout_cycles * 4096);
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/*
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* Derive NFC ideal delay from {3}:
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*
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* (tREA + 4000 - tRP) * 8
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* RDN_DELAY = -----------------------
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* RP
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*/
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if (period_ps > dll_threshold_ps) {
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use_half_period = true;
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reference_period_ps = period_ps / 2;
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} else {
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use_half_period = false;
|
||||
reference_period_ps = period_ps;
|
||||
}
|
||||
|
||||
tRP_ps = data_setup_cycles * period_ps;
|
||||
sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8;
|
||||
if (sample_delay_ps > 0)
|
||||
sample_delay_factor = sample_delay_ps / reference_period_ps;
|
||||
else
|
||||
sample_delay_factor = 0;
|
||||
|
||||
hw->ctrl1n = BF_GPMI_CTRL1_WRN_DLY_SEL(wrn_dly_sel);
|
||||
if (sample_delay_factor)
|
||||
hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) |
|
||||
BM_GPMI_CTRL1_DLL_ENABLE |
|
||||
(use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0);
|
||||
}
|
||||
|
||||
void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
|
||||
{
|
||||
struct gpmi_nfc_hardware_timing *hw = &this->hw;
|
||||
struct resources *r = &this->resources;
|
||||
void __iomem *gpmi_regs = r->gpmi_regs;
|
||||
unsigned int dll_wait_time_us;
|
||||
|
||||
clk_set_rate(r->clock[0], hw->clk_rate);
|
||||
|
||||
writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0);
|
||||
writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1);
|
||||
|
||||
/*
|
||||
* Clear several CTRL1 fields, DLL must be disabled when setting
|
||||
* RDN_DELAY or HALF_PERIOD.
|
||||
*/
|
||||
writel(BM_GPMI_CTRL1_CLEAR_MASK, gpmi_regs + HW_GPMI_CTRL1_CLR);
|
||||
writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET);
|
||||
|
||||
/* Wait 64 clock cycles before using the GPMI after enabling the DLL */
|
||||
dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64;
|
||||
if (!dll_wait_time_us)
|
||||
dll_wait_time_us = 1;
|
||||
|
||||
/* Wait for the DLL to settle. */
|
||||
udelay(dll_wait_time_us);
|
||||
}
|
||||
|
||||
int gpmi_setup_data_interface(struct nand_chip *chip, int chipnr,
|
||||
const struct nand_data_interface *conf)
|
||||
{
|
||||
struct gpmi_nand_data *this = nand_get_controller_data(chip);
|
||||
const struct nand_sdr_timings *sdr;
|
||||
|
||||
/* Retrieve required NAND timings */
|
||||
sdr = nand_get_sdr_timings(conf);
|
||||
if (IS_ERR(sdr))
|
||||
return PTR_ERR(sdr);
|
||||
|
||||
/* Only MX6 GPMI controller can reach EDO timings */
|
||||
if (sdr->tRC_min <= 25000 && !GPMI_IS_MX6(this))
|
||||
return -ENOTSUPP;
|
||||
|
||||
/* Stop here if this call was just a check */
|
||||
if (chipnr < 0)
|
||||
return 0;
|
||||
|
||||
/* Do the actual derivation of the controller timings */
|
||||
gpmi_nfc_compute_timings(this, sdr);
|
||||
|
||||
this->hw.must_apply_timings = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Clears a BCH interrupt. */
|
||||
void gpmi_clear_bch(struct gpmi_nand_data *this)
|
||||
{
|
||||
struct resources *r = &this->resources;
|
||||
writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
|
||||
}
|
||||
|
||||
/* Returns the Ready/Busy status of the given chip. */
|
||||
int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
|
||||
{
|
||||
struct resources *r = &this->resources;
|
||||
uint32_t mask = 0;
|
||||
uint32_t reg = 0;
|
||||
|
||||
if (GPMI_IS_MX23(this)) {
|
||||
mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
|
||||
reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
|
||||
} else if (GPMI_IS_MX28(this) || GPMI_IS_MX6(this)) {
|
||||
/*
|
||||
* In the imx6, all the ready/busy pins are bound
|
||||
* together. So we only need to check chip 0.
|
||||
*/
|
||||
if (GPMI_IS_MX6(this))
|
||||
chip = 0;
|
||||
|
||||
/* MX28 shares the same R/B register as MX6Q. */
|
||||
mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
|
||||
reg = readl(r->gpmi_regs + HW_GPMI_STAT);
|
||||
} else
|
||||
dev_err(this->dev, "unknown arch.\n");
|
||||
return reg & mask;
|
||||
}
|
||||
|
||||
int gpmi_send_command(struct gpmi_nand_data *this)
|
||||
{
|
||||
struct dma_chan *channel = get_dma_chan(this);
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
struct scatterlist *sgl;
|
||||
int chip = this->current_chip;
|
||||
int ret;
|
||||
u32 pio[3];
|
||||
|
||||
/* [1] send out the PIO words */
|
||||
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
|
||||
| BM_GPMI_CTRL0_WORD_LENGTH
|
||||
| BF_GPMI_CTRL0_CS(chip, this)
|
||||
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
||||
| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
|
||||
| BM_GPMI_CTRL0_ADDRESS_INCREMENT
|
||||
| BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
|
||||
pio[1] = pio[2] = 0;
|
||||
desc = dmaengine_prep_slave_sg(channel,
|
||||
(struct scatterlist *)pio,
|
||||
ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [2] send out the COMMAND + ADDRESS string stored in @buffer */
|
||||
sgl = &this->cmd_sgl;
|
||||
|
||||
sg_init_one(sgl, this->cmd_buffer, this->command_length);
|
||||
dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
|
||||
desc = dmaengine_prep_slave_sg(channel,
|
||||
sgl, 1, DMA_MEM_TO_DEV,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [3] submit the DMA */
|
||||
ret = start_dma_without_bch_irq(this, desc);
|
||||
|
||||
dma_unmap_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int gpmi_send_data(struct gpmi_nand_data *this, const void *buf, int len)
|
||||
{
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
struct dma_chan *channel = get_dma_chan(this);
|
||||
int chip = this->current_chip;
|
||||
int ret;
|
||||
uint32_t command_mode;
|
||||
uint32_t address;
|
||||
u32 pio[2];
|
||||
|
||||
/* [1] PIO */
|
||||
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
|
||||
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
||||
|
||||
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
||||
| BM_GPMI_CTRL0_WORD_LENGTH
|
||||
| BF_GPMI_CTRL0_CS(chip, this)
|
||||
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
||||
| BF_GPMI_CTRL0_ADDRESS(address)
|
||||
| BF_GPMI_CTRL0_XFER_COUNT(len);
|
||||
pio[1] = 0;
|
||||
desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
|
||||
ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [2] send DMA request */
|
||||
prepare_data_dma(this, buf, len, DMA_TO_DEVICE);
|
||||
desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
|
||||
1, DMA_MEM_TO_DEV,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [3] submit the DMA */
|
||||
ret = start_dma_without_bch_irq(this, desc);
|
||||
|
||||
dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_TO_DEVICE);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int gpmi_read_data(struct gpmi_nand_data *this, void *buf, int len)
|
||||
{
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
struct dma_chan *channel = get_dma_chan(this);
|
||||
int chip = this->current_chip;
|
||||
int ret;
|
||||
u32 pio[2];
|
||||
bool direct;
|
||||
|
||||
/* [1] : send PIO */
|
||||
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
|
||||
| BM_GPMI_CTRL0_WORD_LENGTH
|
||||
| BF_GPMI_CTRL0_CS(chip, this)
|
||||
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
||||
| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
|
||||
| BF_GPMI_CTRL0_XFER_COUNT(len);
|
||||
pio[1] = 0;
|
||||
desc = dmaengine_prep_slave_sg(channel,
|
||||
(struct scatterlist *)pio,
|
||||
ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [2] : send DMA request */
|
||||
direct = prepare_data_dma(this, buf, len, DMA_FROM_DEVICE);
|
||||
desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
|
||||
1, DMA_DEV_TO_MEM,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [3] : submit the DMA */
|
||||
|
||||
ret = start_dma_without_bch_irq(this, desc);
|
||||
|
||||
dma_unmap_sg(this->dev, &this->data_sgl, 1, DMA_FROM_DEVICE);
|
||||
if (!direct)
|
||||
memcpy(buf, this->data_buffer_dma, len);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int gpmi_send_page(struct gpmi_nand_data *this,
|
||||
dma_addr_t payload, dma_addr_t auxiliary)
|
||||
{
|
||||
struct bch_geometry *geo = &this->bch_geometry;
|
||||
uint32_t command_mode;
|
||||
uint32_t address;
|
||||
uint32_t ecc_command;
|
||||
uint32_t buffer_mask;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
struct dma_chan *channel = get_dma_chan(this);
|
||||
int chip = this->current_chip;
|
||||
u32 pio[6];
|
||||
|
||||
/* A DMA descriptor that does an ECC page read. */
|
||||
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
|
||||
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
||||
ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
|
||||
buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
|
||||
BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
|
||||
|
||||
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
||||
| BM_GPMI_CTRL0_WORD_LENGTH
|
||||
| BF_GPMI_CTRL0_CS(chip, this)
|
||||
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
||||
| BF_GPMI_CTRL0_ADDRESS(address)
|
||||
| BF_GPMI_CTRL0_XFER_COUNT(0);
|
||||
pio[1] = 0;
|
||||
pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
|
||||
| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
|
||||
| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
|
||||
pio[3] = geo->page_size;
|
||||
pio[4] = payload;
|
||||
pio[5] = auxiliary;
|
||||
|
||||
desc = dmaengine_prep_slave_sg(channel,
|
||||
(struct scatterlist *)pio,
|
||||
ARRAY_SIZE(pio), DMA_TRANS_NONE,
|
||||
DMA_CTRL_ACK);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
return start_dma_with_bch_irq(this, desc);
|
||||
}
|
||||
|
||||
int gpmi_read_page(struct gpmi_nand_data *this,
|
||||
dma_addr_t payload, dma_addr_t auxiliary)
|
||||
{
|
||||
struct bch_geometry *geo = &this->bch_geometry;
|
||||
uint32_t command_mode;
|
||||
uint32_t address;
|
||||
uint32_t ecc_command;
|
||||
uint32_t buffer_mask;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
struct dma_chan *channel = get_dma_chan(this);
|
||||
int chip = this->current_chip;
|
||||
u32 pio[6];
|
||||
|
||||
/* [1] Wait for the chip to report ready. */
|
||||
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
|
||||
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
||||
|
||||
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
||||
| BM_GPMI_CTRL0_WORD_LENGTH
|
||||
| BF_GPMI_CTRL0_CS(chip, this)
|
||||
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
||||
| BF_GPMI_CTRL0_ADDRESS(address)
|
||||
| BF_GPMI_CTRL0_XFER_COUNT(0);
|
||||
pio[1] = 0;
|
||||
desc = dmaengine_prep_slave_sg(channel,
|
||||
(struct scatterlist *)pio, 2,
|
||||
DMA_TRANS_NONE, 0);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [2] Enable the BCH block and read. */
|
||||
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
|
||||
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
||||
ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
|
||||
buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
|
||||
| BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
|
||||
|
||||
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
||||
| BM_GPMI_CTRL0_WORD_LENGTH
|
||||
| BF_GPMI_CTRL0_CS(chip, this)
|
||||
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
||||
| BF_GPMI_CTRL0_ADDRESS(address)
|
||||
| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
|
||||
|
||||
pio[1] = 0;
|
||||
pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
|
||||
| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
|
||||
| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
|
||||
pio[3] = geo->page_size;
|
||||
pio[4] = payload;
|
||||
pio[5] = auxiliary;
|
||||
desc = dmaengine_prep_slave_sg(channel,
|
||||
(struct scatterlist *)pio,
|
||||
ARRAY_SIZE(pio), DMA_TRANS_NONE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [3] Disable the BCH block */
|
||||
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
|
||||
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
||||
|
||||
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
||||
| BM_GPMI_CTRL0_WORD_LENGTH
|
||||
| BF_GPMI_CTRL0_CS(chip, this)
|
||||
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
||||
| BF_GPMI_CTRL0_ADDRESS(address)
|
||||
| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
|
||||
pio[1] = 0;
|
||||
pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
|
||||
desc = dmaengine_prep_slave_sg(channel,
|
||||
(struct scatterlist *)pio, 3,
|
||||
DMA_TRANS_NONE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
/* [4] submit the DMA */
|
||||
return start_dma_with_bch_irq(this, desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* gpmi_copy_bits - copy bits from one memory region to another
|
||||
* @dst: destination buffer
|
||||
* @dst_bit_off: bit offset we're starting to write at
|
||||
* @src: source buffer
|
||||
* @src_bit_off: bit offset we're starting to read from
|
||||
* @nbits: number of bits to copy
|
||||
*
|
||||
* This functions copies bits from one memory region to another, and is used by
|
||||
* the GPMI driver to copy ECC sections which are not guaranteed to be byte
|
||||
* aligned.
|
||||
*
|
||||
* src and dst should not overlap.
|
||||
*
|
||||
*/
|
||||
void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
|
||||
const u8 *src, size_t src_bit_off,
|
||||
size_t nbits)
|
||||
{
|
||||
size_t i;
|
||||
size_t nbytes;
|
||||
u32 src_buffer = 0;
|
||||
size_t bits_in_src_buffer = 0;
|
||||
|
||||
if (!nbits)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Move src and dst pointers to the closest byte pointer and store bit
|
||||
* offsets within a byte.
|
||||
*/
|
||||
src += src_bit_off / 8;
|
||||
src_bit_off %= 8;
|
||||
|
||||
dst += dst_bit_off / 8;
|
||||
dst_bit_off %= 8;
|
||||
|
||||
/*
|
||||
* Initialize the src_buffer value with bits available in the first
|
||||
* byte of data so that we end up with a byte aligned src pointer.
|
||||
*/
|
||||
if (src_bit_off) {
|
||||
src_buffer = src[0] >> src_bit_off;
|
||||
if (nbits >= (8 - src_bit_off)) {
|
||||
bits_in_src_buffer += 8 - src_bit_off;
|
||||
} else {
|
||||
src_buffer &= GENMASK(nbits - 1, 0);
|
||||
bits_in_src_buffer += nbits;
|
||||
}
|
||||
nbits -= bits_in_src_buffer;
|
||||
src++;
|
||||
}
|
||||
|
||||
/* Calculate the number of bytes that can be copied from src to dst. */
|
||||
nbytes = nbits / 8;
|
||||
|
||||
/* Try to align dst to a byte boundary. */
|
||||
if (dst_bit_off) {
|
||||
if (bits_in_src_buffer < (8 - dst_bit_off) && nbytes) {
|
||||
src_buffer |= src[0] << bits_in_src_buffer;
|
||||
bits_in_src_buffer += 8;
|
||||
src++;
|
||||
nbytes--;
|
||||
}
|
||||
|
||||
if (bits_in_src_buffer >= (8 - dst_bit_off)) {
|
||||
dst[0] &= GENMASK(dst_bit_off - 1, 0);
|
||||
dst[0] |= src_buffer << dst_bit_off;
|
||||
src_buffer >>= (8 - dst_bit_off);
|
||||
bits_in_src_buffer -= (8 - dst_bit_off);
|
||||
dst_bit_off = 0;
|
||||
dst++;
|
||||
if (bits_in_src_buffer > 7) {
|
||||
bits_in_src_buffer -= 8;
|
||||
dst[0] = src_buffer;
|
||||
dst++;
|
||||
src_buffer >>= 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!bits_in_src_buffer && !dst_bit_off) {
|
||||
/*
|
||||
* Both src and dst pointers are byte aligned, thus we can
|
||||
* just use the optimized memcpy function.
|
||||
*/
|
||||
if (nbytes)
|
||||
memcpy(dst, src, nbytes);
|
||||
} else {
|
||||
/*
|
||||
* src buffer is not byte aligned, hence we have to copy each
|
||||
* src byte to the src_buffer variable before extracting a byte
|
||||
* to store in dst.
|
||||
*/
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
src_buffer |= src[i] << bits_in_src_buffer;
|
||||
dst[i] = src_buffer;
|
||||
src_buffer >>= 8;
|
||||
}
|
||||
}
|
||||
/* Update dst and src pointers */
|
||||
dst += nbytes;
|
||||
src += nbytes;
|
||||
|
||||
/*
|
||||
* nbits is the number of remaining bits. It should not exceed 8 as
|
||||
* we've already copied as much bytes as possible.
|
||||
*/
|
||||
nbits %= 8;
|
||||
|
||||
/*
|
||||
* If there's no more bits to copy to the destination and src buffer
|
||||
* was already byte aligned, then we're done.
|
||||
*/
|
||||
if (!nbits && !bits_in_src_buffer)
|
||||
return;
|
||||
|
||||
/* Copy the remaining bits to src_buffer */
|
||||
if (nbits)
|
||||
src_buffer |= (*src & GENMASK(nbits - 1, 0)) <<
|
||||
bits_in_src_buffer;
|
||||
bits_in_src_buffer += nbits;
|
||||
|
||||
/*
|
||||
* In case there were not enough bits to get a byte aligned dst buffer
|
||||
* prepare the src_buffer variable to match the dst organization (shift
|
||||
* src_buffer by dst_bit_off and retrieve the least significant bits
|
||||
* from dst).
|
||||
*/
|
||||
if (dst_bit_off)
|
||||
src_buffer = (src_buffer << dst_bit_off) |
|
||||
(*dst & GENMASK(dst_bit_off - 1, 0));
|
||||
bits_in_src_buffer += dst_bit_off;
|
||||
|
||||
/*
|
||||
* Keep most significant bits from dst if we end up with an unaligned
|
||||
* number of bits.
|
||||
*/
|
||||
nbytes = bits_in_src_buffer / 8;
|
||||
if (bits_in_src_buffer % 8) {
|
||||
src_buffer |= (dst[nbytes] &
|
||||
GENMASK(7, bits_in_src_buffer % 8)) <<
|
||||
(nbytes * 8);
|
||||
nbytes++;
|
||||
}
|
||||
|
||||
/* Copy the remaining bytes to dst */
|
||||
for (i = 0; i < nbytes; i++) {
|
||||
dst[i] = src_buffer;
|
||||
src_buffer >>= 8;
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -159,40 +159,6 @@ struct gpmi_nand_data {
|
|||
void *private;
|
||||
};
|
||||
|
||||
/* Common Services */
|
||||
int common_nfc_set_geometry(struct gpmi_nand_data *);
|
||||
struct dma_chan *get_dma_chan(struct gpmi_nand_data *);
|
||||
bool prepare_data_dma(struct gpmi_nand_data *, const void *buf, int len,
|
||||
enum dma_data_direction dr);
|
||||
int start_dma_without_bch_irq(struct gpmi_nand_data *,
|
||||
struct dma_async_tx_descriptor *);
|
||||
int start_dma_with_bch_irq(struct gpmi_nand_data *,
|
||||
struct dma_async_tx_descriptor *);
|
||||
|
||||
/* GPMI-NAND helper function library */
|
||||
int gpmi_init(struct gpmi_nand_data *);
|
||||
void gpmi_clear_bch(struct gpmi_nand_data *);
|
||||
void gpmi_dump_info(struct gpmi_nand_data *);
|
||||
int bch_set_geometry(struct gpmi_nand_data *);
|
||||
int gpmi_is_ready(struct gpmi_nand_data *, unsigned chip);
|
||||
int gpmi_send_command(struct gpmi_nand_data *);
|
||||
int gpmi_enable_clk(struct gpmi_nand_data *this);
|
||||
int gpmi_disable_clk(struct gpmi_nand_data *this);
|
||||
int gpmi_setup_data_interface(struct nand_chip *chip, int chipnr,
|
||||
const struct nand_data_interface *conf);
|
||||
void gpmi_nfc_apply_timings(struct gpmi_nand_data *this);
|
||||
int gpmi_read_data(struct gpmi_nand_data *, void *buf, int len);
|
||||
int gpmi_send_data(struct gpmi_nand_data *, const void *buf, int len);
|
||||
|
||||
int gpmi_send_page(struct gpmi_nand_data *,
|
||||
dma_addr_t payload, dma_addr_t auxiliary);
|
||||
int gpmi_read_page(struct gpmi_nand_data *,
|
||||
dma_addr_t payload, dma_addr_t auxiliary);
|
||||
|
||||
void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
|
||||
const u8 *src, size_t src_bit_off,
|
||||
size_t nbits);
|
||||
|
||||
/* BCH : Status Block Completion Codes */
|
||||
#define STATUS_GOOD 0x00
|
||||
#define STATUS_ERASED 0xff
|
||||
|
|
|
|||
Loading…
Reference in New Issue