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This pull request contains Broadcom ARM64-based SoCs Device Tree changes for 

4.14, please pull the following:
 
 - Scott moves all the Northstar 2 DTS files into a sub-directory to be consistent
   with what was done for stingray and to future proof the addition of new board
   DTS files
 
 - Velibor adds the ARM CCN-502 interconnect DT node to the Stingray SoC
   DTS include file
 
 - Srinath adds the MDIO multiplexer and SATA nodes to the Stingray DTS
   include files
 
 - Anup adds the SP804 timers, FlexRM (mailbox) and RAID engine DT nodes
   to the Stingray DTS include files
 
 - Abishek adds the BGMAC (Ethernet controller) node to the Stingray DTS
   files
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Merge tag 'arm-soc/for-4.14/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64

Pull "Broadcom devicetree-arm64 changes for 4.14" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs Device Tree changes for
4.14, please pull the following:

- Scott moves all the Northstar 2 DTS files into a sub-directory to be consistent
  with what was done for stingray and to future proof the addition of new board
  DTS files

- Velibor adds the ARM CCN-502 interconnect DT node to the Stingray SoC
  DTS include file

- Srinath adds the MDIO multiplexer and SATA nodes to the Stingray DTS
  include files

- Anup adds the SP804 timers, FlexRM (mailbox) and RAID engine DT nodes
  to the Stingray DTS include files

- Abishek adds the BGMAC (Ethernet controller) node to the Stingray DTS
  files

* tag 'arm-soc/for-4.14/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: Add SBA-RAID DT nodes for Stingray SoC
  arm64: dts: Add FlexRM DT nodes for Stingray
  arm64: dts: Add SATA DT nodes for Stingray SoC
  arm64: dts: Add DT node to enable BGMAC driver on Stingray
  arm64: dts: Add sp804 DT nodes for Stingray SoC
  arm64: dts: Add MDIO multiplexer DT node for Stingray
  arm64: dts: Enable stats for CCN-502 interconnect on Stingray
  arm64: dts: move ns2 into northstar2 directory
This commit is contained in:
Arnd Bergmann 2017-08-18 22:43:51 +02:00
parent 36d0f13881 63b2ff6aa6
commit 3004a512ed
12 changed files with 626 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -1,7 +1,7 @@
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb ns2-xmc.dtb
dts-dirs := stingray
dts-dirs += northstar2
dts-dirs += stingray
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

6
arch/arm64/boot/dts/broadcom/northstar2/Makefile Normal file
View File

@ -0,0 +1,6 @@
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-xmc.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

0
arch/arm64/boot/dts/broadcom/ns2-clock.dtsi → arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi
View File

0
arch/arm64/boot/dts/broadcom/ns2-svk.dts → arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts
View File

0
arch/arm64/boot/dts/broadcom/ns2-xmc.dts → arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts
View File

0
arch/arm64/boot/dts/broadcom/ns2.dtsi → arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View File

78
arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
View File

@ -72,6 +72,78 @@
<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
};
&sata0 {
status = "okay";
};
&sata_phy0{
status = "okay";
};
&sata1 {
status = "okay";
};
&sata_phy1{
status = "okay";
};
&sata2 {
status = "okay";
};
&sata_phy2{
status = "okay";
};
&sata3 {
status = "okay";
};
&sata_phy3{
status = "okay";
};
&sata4 {
status = "okay";
};
&sata_phy4{
status = "okay";
};
&sata5 {
status = "okay";
};
&sata_phy5{
status = "okay";
};
&sata6 {
status = "okay";
};
&sata_phy6{
status = "okay";
};
&sata7 {
status = "okay";
};
&sata_phy7{
status = "okay";
};
&mdio_mux_iproc {
mdio@10 {
gphy0: eth-phy@10 {
reg = <0x10>;
};
};
};
&uart1 {
status = "okay";
};
@ -102,6 +174,12 @@
};
};
&enet {
phy-mode = "rgmii-id";
phy-handle = <&gphy0>;
status = "okay";
};
&nand {
status = "ok";
nandcs@0 {

4
arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
View File

@ -39,6 +39,10 @@
model = "Stingray Combo SVK (BCM958742K)";
};
&gphy0 {
enet-phy-lane-swap;
};
&uart2 {
status = "okay";
};

4
arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
View File

@ -38,3 +38,7 @@
compatible = "brcm,bcm958742t", "brcm,stingray";
model = "Stingray SST100 (BCM958742T)";
};
&gphy0 {
enet-phy-lane-swap;
};

118
arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi Normal file
View File

@ -0,0 +1,118 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
fs4: fs4 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x67000000 0x00800000>;
crypto_mbox: crypto_mbox@00000000 {
compatible = "brcm,iproc-flexrm-mbox";
reg = <0x00000000 0x200000>;
msi-parent = <&gic_its 0x4100>;
#mbox-cells = <3>;
dma-coherent;
};
raid_mbox: raid_mbox@00400000 {
compatible = "brcm,iproc-flexrm-mbox";
reg = <0x00400000 0x200000>;
dma-coherent;
msi-parent = <&gic_its 0x4300>;
#mbox-cells = <3>;
};
raid0: raid@0 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 0 0x1 0xff00>,
<&raid_mbox 1 0x1 0xff00>,
<&raid_mbox 2 0x1 0xff00>,
<&raid_mbox 3 0x1 0xff00>;
};
raid1: raid@1 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 4 0x1 0xff00>,
<&raid_mbox 5 0x1 0xff00>,
<&raid_mbox 6 0x1 0xff00>,
<&raid_mbox 7 0x1 0xff00>;
};
raid2: raid@2 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 8 0x1 0xff00>,
<&raid_mbox 9 0x1 0xff00>,
<&raid_mbox 10 0x1 0xff00>,
<&raid_mbox 11 0x1 0xff00>;
};
raid3: raid@3 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 12 0x1 0xff00>,
<&raid_mbox 13 0x1 0xff00>,
<&raid_mbox 14 0x1 0xff00>,
<&raid_mbox 15 0x1 0xff00>;
};
raid4: raid@4 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 16 0x1 0xff00>,
<&raid_mbox 17 0x1 0xff00>,
<&raid_mbox 18 0x1 0xff00>,
<&raid_mbox 19 0x1 0xff00>;
};
raid5: raid@5 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 20 0x1 0xff00>,
<&raid_mbox 21 0x1 0xff00>,
<&raid_mbox 22 0x1 0xff00>,
<&raid_mbox 23 0x1 0xff00>;
};
raid6: raid@6 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 24 0x1 0xff00>,
<&raid_mbox 25 0x1 0xff00>,
<&raid_mbox 26 0x1 0xff00>,
<&raid_mbox 27 0x1 0xff00>;
};
raid7: raid@7 {
compatible = "brcm,iproc-sba-v2";
mboxes = <&raid_mbox 28 0x1 0xff00>,
<&raid_mbox 29 0x1 0xff00>,
<&raid_mbox 30 0x1 0xff00>,
<&raid_mbox 31 0x1 0xff00>;
};
};

278
arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi Normal file
View File

@ -0,0 +1,278 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016-2017 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
sata {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x67d00000 0x00800000>;
sata0: ahci@00210000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00210000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata0_port0: sata-port@0 {
reg = <0>;
phys = <&sata0_phy0>;
phy-names = "sata-phy";
};
};
sata_phy0: sata_phy@00212100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00212100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata0_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
sata1: ahci@00310000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00310000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata1_port0: sata-port@0 {
reg = <0>;
phys = <&sata1_phy0>;
phy-names = "sata-phy";
};
};
sata_phy1: sata_phy@00312100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00312100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata1_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
sata2: ahci@00120000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00120000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata2_port0: sata-port@0 {
reg = <0>;
phys = <&sata2_phy0>;
phy-names = "sata-phy";
};
};
sata_phy2: sata_phy@00122100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00122100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata2_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
sata3: ahci@00130000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00130000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata3_port0: sata-port@0 {
reg = <0>;
phys = <&sata3_phy0>;
phy-names = "sata-phy";
};
};
sata_phy3: sata_phy@00132100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00132100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata3_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
sata4: ahci@00330000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00330000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata4_port0: sata-port@0 {
reg = <0>;
phys = <&sata4_phy0>;
phy-names = "sata-phy";
};
};
sata_phy4: sata_phy@00332100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00332100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata4_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
sata5: ahci@00400000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00400000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata5_port0: sata-port@0 {
reg = <0>;
phys = <&sata5_phy0>;
phy-names = "sata-phy";
};
};
sata_phy5: sata_phy@00402100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00402100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata5_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
sata6: ahci@00410000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00410000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata6_port0: sata-port@0 {
reg = <0>;
phys = <&sata6_phy0>;
phy-names = "sata-phy";
};
};
sata_phy6: sata_phy@00412100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00412100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata6_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
sata7: ahci@00420000 {
compatible = "brcm,iproc-ahci", "generic-ahci";
reg = <0x00420000 0x1000>;
reg-names = "ahci";
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata7_port0: sata-port@0 {
reg = <0>;
phys = <&sata7_phy0>;
phy-names = "sata-phy";
};
};
sata_phy7: sata_phy@00422100 {
compatible = "brcm,iproc-sr-sata-phy";
reg = <0x00422100 0x1000>;
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
sata7_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
};

136
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@ -152,6 +152,12 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x61000000 0x05000000>;
ccn: ccn@00000000 {
compatible = "arm,ccn-502";
reg = <0x00000000 0x900000>;
interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@02c00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
@ -261,6 +267,9 @@
};
};
#include "stingray-fs4.dtsi"
#include "stingray-sata.dtsi"
hsls {
compatible = "simple-bus";
#address-cells = <1>;
@ -269,6 +278,37 @@
#include "stingray-pinctrl.dtsi"
mdio_mux_iproc: mdio-mux@0002023c {
compatible = "brcm,mdio-mux-iproc";
reg = <0x0002023c 0x14>;
#address-cells = <1>;
#size-cells = <0>;
mdio@0 { /* PCIe serdes */
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@2 { /* SATA */
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@3 { /* USB */
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio@10 { /* RGMII */
reg = <0x10>;
#address-cells = <1>;
#size-cells = <0>;
};
};
pwm: pwm@00010000 {
compatible = "brcm,iproc-pwm";
reg = <0x00010000 0x1000>;
@ -277,6 +317,93 @@
status = "disabled";
};
timer0: timer@00030000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00030000 0x1000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer1: timer@00040000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00040000 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer2: timer@00050000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00050000 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer3: timer@00060000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00060000 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer4: timer@00070000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00070000 0x1000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer5: timer@00080000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00080000 0x1000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer6: timer@00090000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x00090000 0x1000>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
timer7: timer@000a0000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x000a0000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>,
<&hsls_25m_div2_clk>,
<&hsls_div4_clk>;
clock-names = "timer1", "timer2", "apb_pclk";
status = "disabled";
};
i2c0: i2c@000b0000 {
compatible = "brcm,iproc-i2c";
reg = <0x000b0000 0x100>;
@ -424,6 +551,15 @@
iommus = <&smmu 0x6000 0x0000>;
};
enet: ethernet@00340000{
compatible = "brcm,amac";
reg = <0x00340000 0x1000>;
reg-names = "amac_base";
dma-coherent;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
status= "disabled";
};
nand: nand@00360000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x00360000 0x600>,