x86/tlb: Move __flush_tlb() out of line
cpu_tlbstate is exported because various TLB-related functions need access to it, but cpu_tlbstate is sensitive information which should only be accessed by well-contained kernel functions and not be directly exposed to modules. As a first step, move __flush_tlb() out of line and hide the native function. The latter can be static when CONFIG_PARAVIRT is disabled. Consolidate the namespace while at it and remove the pointless extra wrapper in the paravirt code. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20200421092559.246130908@linutronix.de
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@ -47,7 +47,9 @@ static inline void slow_down_io(void)
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#endif
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}
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static inline void __flush_tlb(void)
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void native_flush_tlb_local(void);
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static inline void __flush_tlb_local(void)
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{
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PVOP_VCALL0(mmu.flush_tlb_user);
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}
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@ -140,12 +140,13 @@ static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
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return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
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}
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void flush_tlb_local(void);
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __flush_tlb() __native_flush_tlb()
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#define __flush_tlb_global() __native_flush_tlb_global()
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#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)
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#define __flush_tlb_global() __native_flush_tlb_global()
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#define __flush_tlb_one_user(addr) __native_flush_tlb_one_user(addr)
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#endif
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struct tlb_context {
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@ -370,24 +371,6 @@ static inline void invalidate_user_asid(u16 asid)
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(unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
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}
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/*
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* flush the entire current user mapping
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*/
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static inline void __native_flush_tlb(void)
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{
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/*
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* Preemption or interrupts must be disabled to protect the access
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* to the per CPU variable and to prevent being preempted between
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* read_cr3() and write_cr3().
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*/
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WARN_ON_ONCE(preemptible());
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invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
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/* If current->mm == NULL then the read_cr3() "borrows" an mm */
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native_write_cr3(__native_read_cr3());
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}
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/*
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* flush everything
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*/
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@ -461,7 +444,7 @@ static inline void __flush_tlb_all(void)
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/*
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* !PGE -> !PCID (setup_pcid()), thus every flush is total.
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*/
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__flush_tlb();
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flush_tlb_local();
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}
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}
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@ -537,8 +520,6 @@ struct flush_tlb_info {
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bool freed_tables;
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};
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#define local_flush_tlb() __flush_tlb()
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#define flush_tlb_mm(mm) \
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flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL, true)
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@ -761,7 +761,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
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/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
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count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
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__flush_tlb();
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flush_tlb_local();
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/* Save MTRR state */
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rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
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@ -778,7 +778,7 @@ static void post_set(void) __releases(set_atomicity_lock)
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{
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/* Flush TLBs (no need to flush caches - they are disabled) */
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count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
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__flush_tlb();
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flush_tlb_local();
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/* Intel (P6) standard MTRRs */
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mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
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@ -160,11 +160,6 @@ unsigned paravirt_patch_insns(void *insn_buff, unsigned len,
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return insn_len;
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}
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static void native_flush_tlb(void)
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{
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__native_flush_tlb();
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}
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/*
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* Global pages have to be flushed a bit differently. Not a real
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* performance problem because this does not happen often.
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@ -359,7 +354,7 @@ struct paravirt_patch_template pv_ops = {
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#endif /* CONFIG_PARAVIRT_XXL */
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/* Mmu ops. */
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.mmu.flush_tlb_user = native_flush_tlb,
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.mmu.flush_tlb_user = native_flush_tlb_local,
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.mmu.flush_tlb_kernel = native_flush_tlb_global,
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.mmu.flush_tlb_one_user = native_flush_tlb_one_user,
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.mmu.flush_tlb_others = native_flush_tlb_others,
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@ -134,7 +134,7 @@ static void __init __sme_early_map_unmap_mem(void *vaddr, unsigned long size,
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size = (size <= PMD_SIZE) ? 0 : size - PMD_SIZE;
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} while (size);
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__native_flush_tlb();
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flush_tlb_local();
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}
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void __init sme_unmap_bootdata(char *real_mode_data)
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@ -18,6 +18,13 @@
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#include "mm_internal.h"
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#ifdef CONFIG_PARAVIRT
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# define STATIC_NOPV
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#else
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# define STATIC_NOPV static
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# define __flush_tlb_local native_flush_tlb_local
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#endif
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/*
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* TLB flushing, formerly SMP-only
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* c/o Linus Torvalds.
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@ -645,7 +652,7 @@ static void flush_tlb_func_common(const struct flush_tlb_info *f,
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trace_tlb_flush(reason, nr_invalidate);
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} else {
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/* Full flush. */
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local_flush_tlb();
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flush_tlb_local();
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if (local)
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count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
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trace_tlb_flush(reason, TLB_FLUSH_ALL);
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@ -883,6 +890,30 @@ unsigned long __get_current_cr3_fast(void)
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}
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EXPORT_SYMBOL_GPL(__get_current_cr3_fast);
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/*
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* Flush the entire current user mapping
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*/
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STATIC_NOPV void native_flush_tlb_local(void)
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{
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/*
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* Preemption or interrupts must be disabled to protect the access
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* to the per CPU variable and to prevent being preempted between
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* read_cr3() and write_cr3().
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*/
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WARN_ON_ONCE(preemptible());
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invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
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/* If current->mm == NULL then the read_cr3() "borrows" an mm */
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native_write_cr3(__native_read_cr3());
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}
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void flush_tlb_local(void)
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{
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__flush_tlb_local();
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}
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EXPORT_SYMBOL_GPL(flush_tlb_local);
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/*
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* arch_tlbbatch_flush() performs a full TLB flush regardless of the active mm.
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* This means that the 'struct flush_tlb_info' that describes which mappings to
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@ -293,7 +293,7 @@ static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
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* This must be a normal message, or retry of a normal message
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*/
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if (msg->address == TLB_FLUSH_ALL) {
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local_flush_tlb();
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flush_tlb_local();
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stat->d_alltlb++;
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} else {
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__flush_tlb_one_user(msg->address);
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