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drm/i915: Capture max frl rate for PCON in dfp cap structure 

HDMI2.1 PCON advertises Max FRL bandwidth supported by the PCON.

This patch captures this in dfp cap structure in intel_dp and uses
this to prune connector modes that cannot be supported by the PCON
and FRL bandwidth.

v2: Addressed review comments from Uma Shankar:
-tweaked the comparison of target bw and pcon frl bw to avoid roundup errors.
-minor modification of field names and comments.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201218103723.30844-9-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal 2020-12-18 16:07:16 +05:30 committed by Jani Nikula
parent 07c9b8634f
commit 2f78347e36
2 changed files with 29 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/i915/display/intel_display_types.h
View File

@ -1432,6 +1432,7 @@ struct intel_dp {
struct { struct {
int min_tmds_clock, max_tmds_clock; int min_tmds_clock, max_tmds_clock;
int max_dotclock; int max_dotclock;
int pcon_max_frl_bw;
u8 max_bpc; u8 max_bpc;
bool ycbcr_444_to_420; bool ycbcr_444_to_420;
} dfp; } dfp;

30
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -716,6 +716,25 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_info *info = &connector->base.display_info; const struct drm_display_info *info = &connector->base.display_info;
int tmds_clock; int tmds_clock;
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
int target_bw;
int max_frl_bw;
int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode);
target_bw = bpp * target_clock;
max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
/* converting bw from Gbps to Kbps*/
max_frl_bw = max_frl_bw * 1000000;
if (target_bw > max_frl_bw)
return MODE_CLOCK_HIGH;
return MODE_OK;
}
if (intel_dp->dfp.max_dotclock && if (intel_dp->dfp.max_dotclock &&
target_clock > intel_dp->dfp.max_dotclock) target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH; return MODE_CLOCK_HIGH;
@ -6480,13 +6499,18 @@ intel_dp_update_dfp(struct intel_dp *intel_dp,
intel_dp->downstream_ports, intel_dp->downstream_ports,
edid); edid);
intel_dp->dfp.pcon_max_frl_bw =
drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
intel_dp->downstream_ports);
drm_dbg_kms(&i915->drm, drm_dbg_kms(&i915->drm,
"[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n", "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
connector->base.base.id, connector->base.name, connector->base.base.id, connector->base.name,
intel_dp->dfp.max_bpc, intel_dp->dfp.max_bpc,
intel_dp->dfp.max_dotclock, intel_dp->dfp.max_dotclock,
intel_dp->dfp.min_tmds_clock, intel_dp->dfp.min_tmds_clock,
intel_dp->dfp.max_tmds_clock); intel_dp->dfp.max_tmds_clock,
intel_dp->dfp.pcon_max_frl_bw);
} }
static void static void
@ -6578,6 +6602,8 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
intel_dp->dfp.min_tmds_clock = 0; intel_dp->dfp.min_tmds_clock = 0;
intel_dp->dfp.max_tmds_clock = 0; intel_dp->dfp.max_tmds_clock = 0;
intel_dp->dfp.pcon_max_frl_bw = 0;
intel_dp->dfp.ycbcr_444_to_420 = false; intel_dp->dfp.ycbcr_444_to_420 = false;
connector->base.ycbcr_420_allowed = false; connector->base.ycbcr_420_allowed = false;
} }