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drm/radeon: clean up encoder dp checks 

Use the proper struct in the union.  That field
has the same offset in every struct, so no functional
change.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2012-09-06 12:26:09 -04:00
parent e971bd5e45
commit 2f6fa79a7e
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/radeon/atombios_encoders.c
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@ -866,14 +866,14 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
else else
args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
args.v3.ucLaneNum = dp_lane_count; args.v3.ucLaneNum = dp_lane_count;
else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
args.v3.ucLaneNum = 8; args.v3.ucLaneNum = 8;
else else
args.v3.ucLaneNum = 4; args.v3.ucLaneNum = 4;
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
args.v3.acConfig.ucDigSel = dig->dig_encoder; args.v3.acConfig.ucDigSel = dig->dig_encoder;
args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
@ -886,14 +886,14 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
else else
args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
args.v4.ucLaneNum = dp_lane_count; args.v4.ucLaneNum = dp_lane_count;
else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
args.v4.ucLaneNum = 8; args.v4.ucLaneNum = 8;
else else
args.v4.ucLaneNum = 4; args.v4.ucLaneNum = 4;
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) { if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
if (dp_clock == 270000) if (dp_clock == 270000)
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
else if (dp_clock == 540000) else if (dp_clock == 540000)