drm/vmwgfx: Command parser fixes for DX
Implement support for a couple of missing commands and fix a command parser error path. Also fix uninitialized devcaps and surface size computation. Signed-off-by: Charmaine Lee <charmainel@vmware.com> Signed-off-by: Sinclair Yeh <syeh@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
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@ -37,6 +37,7 @@ struct vmw_user_context {
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struct vmw_cmdbuf_res_manager *man;
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struct vmw_resource *cotables[SVGA_COTABLE_DX10_MAX];
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spinlock_t cotable_lock;
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struct vmw_dma_buffer *dx_query_mob;
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};
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static void vmw_user_context_free(struct vmw_resource *res);
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@ -553,6 +553,7 @@ static int vmw_resources_reserve(struct vmw_sw_context *sw_context)
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return ret;
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}
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}
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return 0;
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}
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@ -2484,6 +2485,63 @@ static int vmw_cmd_dx_view_define(struct vmw_private *dev_priv,
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&sw_context->staged_cmd_res);
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}
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/**
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* vmw_cmd_dx_set_so_targets - Validate an
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* SVGA_3D_CMD_DX_SET_SOTARGETS command.
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*
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* @dev_priv: Pointer to a device private struct.
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* @sw_context: The software context being used for this batch.
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* @header: Pointer to the command header in the command stream.
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*/
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static int vmw_cmd_dx_set_so_targets(struct vmw_private *dev_priv,
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struct vmw_sw_context *sw_context,
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SVGA3dCmdHeader *header)
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{
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struct vmw_resource_val_node *ctx_node = sw_context->dx_ctx_node;
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struct vmw_ctx_bindinfo_so binding;
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struct vmw_resource_val_node *res_node;
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struct {
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SVGA3dCmdHeader header;
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SVGA3dCmdDXSetSOTargets body;
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SVGA3dSoTarget targets[];
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} *cmd;
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int i, ret, num;
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if (unlikely(ctx_node == NULL)) {
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DRM_ERROR("DX Context not set.\n");
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return -EINVAL;
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}
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cmd = container_of(header, typeof(*cmd), header);
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num = (cmd->header.size - sizeof(cmd->body)) /
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sizeof(SVGA3dSoTarget);
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if (num > SVGA3D_DX_MAX_SOTARGETS) {
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DRM_ERROR("Invalid DX SO binding.\n");
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return -EINVAL;
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}
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for (i = 0; i < num; i++) {
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ret = vmw_cmd_res_check(dev_priv, sw_context, vmw_res_surface,
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user_surface_converter,
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&cmd->targets[i].sid, &res_node);
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if (unlikely(ret != 0))
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return ret;
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binding.bi.ctx = ctx_node->res;
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binding.bi.res = ((res_node) ? res_node->res : NULL);
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binding.bi.bt = vmw_ctx_binding_so,
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binding.offset = cmd->targets[i].offset;
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binding.size = cmd->targets[i].sizeInBytes;
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binding.slot = i;
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vmw_binding_add(ctx_node->staged_bindings, &binding.bi,
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0, binding.slot);
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}
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return 0;
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}
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static int vmw_cmd_dx_so_define(struct vmw_private *dev_priv,
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struct vmw_sw_context *sw_context,
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SVGA3dCmdHeader *header)
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@ -2971,11 +3029,17 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
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&vmw_cmd_dx_set_shader_res, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SHADER, &vmw_cmd_dx_set_shader,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INSTANCED, &vmw_cmd_invalid,
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SAMPLERS, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED, &vmw_cmd_invalid,
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_AUTO, &vmw_cmd_invalid,
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INDEXED, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INSTANCED, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED,
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&vmw_cmd_dx_cid_check, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DRAW_AUTO, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS,
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&vmw_cmd_dx_set_vertex_buffers, true, false, true),
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@ -2985,11 +3049,10 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
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&vmw_cmd_dx_set_rendertargets, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_BLEND_STATE, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE,
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&vmw_cmd_dx_cid_check,
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true, false, true),
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&vmw_cmd_dx_cid_check, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_RASTERIZER_STATE,
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&vmw_cmd_dx_cid_check, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DEFINE_QUERY, &vmw_cmd_invalid,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_QUERY, &vmw_cmd_invalid,
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@ -3066,8 +3129,10 @@ static const struct vmw_cmd_entry vmw_cmd_entries[SVGA_3D_CMD_MAX] = {
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&vmw_cmd_dx_so_define, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT,
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&vmw_cmd_dx_cid_check, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_STREAMOUTPUT, &vmw_cmd_invalid,
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_STREAMOUTPUT, &vmw_cmd_dx_cid_check,
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true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_SOTARGETS,
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&vmw_cmd_dx_set_so_targets, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_INPUT_LAYOUT,
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&vmw_cmd_dx_cid_check, true, false, true),
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VMW_CMD_DEF(SVGA_3D_CMD_DX_SET_TOPOLOGY,
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@ -3692,11 +3757,18 @@ int vmw_execbuf_process(struct drm_file *file_priv,
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ret = vmw_cmd_check_all(dev_priv, sw_context, kernel_commands,
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command_size);
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/*
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* Merge the resource lists before checking the return status
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* from vmd_cmd_check_all so that all the open hashtabs will
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* be handled properly even if vmw_cmd_check_all fails.
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*/
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list_splice_init(&sw_context->ctx_resource_list,
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&sw_context->resource_list);
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if (unlikely(ret != 0))
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goto out_err_nores;
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list_splice_init(&sw_context->ctx_resource_list,
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&sw_context->resource_list);
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ret = vmw_resources_reserve(sw_context);
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if (unlikely(ret != 0))
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goto out_err_nores;
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@ -196,8 +196,8 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data,
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uint32_t *bounce32 = (uint32_t *) bounce;
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num = size / sizeof(uint32_t);
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if (num > SVGA3D_DEVCAP_DX)
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num = SVGA3D_DEVCAP_DX;
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if (num > SVGA3D_DEVCAP_MAX)
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num = SVGA3D_DEVCAP_MAX;
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spin_lock(&dev_priv->cap_lock);
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for (i = 0; i < num; ++i) {
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@ -1533,6 +1533,7 @@ int vmw_surface_gb_priv_define(struct drm_device *dev,
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srf->offsets = NULL;
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srf->base_size = size;
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srf->autogen_filter = SVGA3D_TEX_FILTER_NONE;
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srf->array_size = array_size;
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srf->multisample_count = multisample_count;
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if (array_size)
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