drm/amd/display: Use MACROS instead of dm_logger
Created MACROS for all log levels. Also Replaced usage of dm_logger_write to the defined MACROS Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
44c6f2e59e
commit
2f3fd67a8a
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@ -3079,7 +3079,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
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opm_object,
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&ext_display_connection_info_tbl) != BP_RESULT_OK) {
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dm_logger_write(bp->base.ctx->logger, LOG_WARNING,
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DC_LOG_WARNING(bp->base.ctx->logger,
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"%s: Failed to read Connection Info Table", __func__);
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return BP_RESULT_UNSUPPORTED;
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}
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@ -239,7 +239,7 @@ static enum bp_result transmitter_control_v1_6(
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if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||
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cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||
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cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {
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dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
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DC_LOG_BIOS(bp->base.ctx->logger, \
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"%s:ps.param.symclk_10khz = %d\n",\
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__func__, ps.param.symclk_10khz);
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}
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@ -331,7 +331,7 @@ static enum bp_result set_pixel_clock_v7(
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(uint8_t) bp->cmd_helper->
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transmitter_color_depth_to_atom(
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bp_params->color_depth);
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dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\
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DC_LOG_BIOS(bp->base.ctx->logger, \
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"%s:program display clock = %d"\
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"colorDepth = %d\n", __func__,\
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bp_params->target_pixel_clock, bp_params->color_depth);
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@ -772,7 +772,7 @@ static enum bp_result set_dce_clock_v2_1(
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*/
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params.param.dceclk_10khz = cpu_to_le32(
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bp_params->target_clock_frequency / 10);
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dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
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DC_LOG_BIOS(bp->base.ctx->logger,
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"%s:target_clock_frequency = %d"\
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"clock_type = %d \n", __func__,\
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bp_params->target_clock_frequency,\
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@ -1242,7 +1242,7 @@ unsigned int dcn_find_dcfclk_suits_all(
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else
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dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000;
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dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
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DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
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"\tdcf_clk for voltage = %d\n", dcf_clk);
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return dcf_clk;
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}
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@ -1441,7 +1441,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
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void dcn_bw_sync_calcs_and_dml(struct dc *dc)
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{
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kernel_fpu_begin();
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dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
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DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
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"sr_exit_time: %d ns\n"
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"sr_enter_plus_exit_time: %d ns\n"
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"urgent_latency: %d ns\n"
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@ -1510,7 +1510,7 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
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dc->dcn_soc->vmm_page_size,
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dc->dcn_soc->dram_clock_change_latency * 1000,
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dc->dcn_soc->return_bus_width);
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dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
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DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
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"rob_buffer_size_in_kbyte: %d\n"
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"det_buffer_size_in_kbyte: %d\n"
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"dpp_output_buffer_pixels: %d\n"
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@ -264,7 +264,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
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/* Only call if supported */
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if (tg->funcs->configure_crc)
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return tg->funcs->configure_crc(tg, ¶m);
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dm_logger_write(dc->ctx->logger, LOG_WARNING, "CRC capture not supported.");
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DC_LOG_WARNING(dc->ctx->logger, "CRC capture not supported.");
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return false;
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}
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@ -297,7 +297,7 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
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if (tg->funcs->get_crc)
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return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
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dm_logger_write(dc->ctx->logger, LOG_WARNING, "CRC capture not supported.");
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DC_LOG_WARNING(dc->ctx->logger, "CRC capture not supported.");
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return false;
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}
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@ -618,7 +618,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
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dc->config = init_params->flags;
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dm_logger_write(dc->ctx->logger, LOG_DC,
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DC_LOG_DC(dc->ctx->logger,
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"Display Core initialized\n");
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@ -888,7 +888,7 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
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if (false == context_changed(dc, context))
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return DC_OK;
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dm_logger_write(dc->ctx->logger, LOG_DC, "%s: %d streams\n",
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DC_LOG_DC(dc->ctx->logger, "%s: %d streams\n",
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__func__, context->stream_count);
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for (i = 0; i < context->stream_count; i++) {
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@ -47,7 +47,7 @@
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#include "dce/dce_11_0_sh_mask.h"
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#define LINK_INFO(...) \
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dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \
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DC_LOG_HW_HOTPLUG(dc_ctx->logger, \
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__VA_ARGS__)
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/*******************************************************************************
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@ -677,11 +677,11 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
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switch (edid_status) {
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case EDID_BAD_CHECKSUM:
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dm_logger_write(link->ctx->logger, LOG_ERROR,
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DC_LOG_ERROR(link->ctx->logger,
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"EDID checksum invalid.\n");
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break;
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case EDID_NO_RESPONSE:
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dm_logger_write(link->ctx->logger, LOG_ERROR,
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DC_LOG_ERROR(link->ctx->logger,
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"No EDID read.\n");
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default:
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break;
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@ -712,7 +712,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
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"%s: [Block %d] ", sink->edid_caps.display_name, i);
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}
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dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
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DC_LOG_DETECTION_EDID_PARSER(link->ctx->logger,
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"%s: "
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"manufacturer_id = %X, "
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"product_id = %X, "
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@ -733,7 +733,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
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sink->edid_caps.audio_mode_count);
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for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
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dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,
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DC_LOG_DETECTION_EDID_PARSER(link->ctx->logger,
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"%s: mode number = %d, "
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"format_code = %d, "
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"channel_count = %d, "
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@ -984,7 +984,7 @@ static bool construct(
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}
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break;
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default:
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dm_logger_write(dc_ctx->logger, LOG_WARNING,
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DC_LOG_WARNING(dc_ctx->logger,
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"Unsupported Connector type:%d!\n", link->link_id.id);
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goto create_fail;
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}
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@ -1175,7 +1175,7 @@ static void dpcd_configure_panel_mode(
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ASSERT(result == DDC_RESULT_SUCESSFULL);
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}
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}
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dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS,
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DC_LOG_DETECTION_DP_CAPS(link->ctx->logger,
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"Link: %d eDP panel mode supported: %d "
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"eDP panel mode enabled: %d \n",
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link->link_index,
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@ -1965,7 +1965,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
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use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
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dm_logger_write(link->ctx->logger, LOG_BACKLIGHT,
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DC_LOG_BACKLIGHT(link->ctx->logger,
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"New Backlight level: %d (0x%X)\n", level, level);
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if (dc_is_embedded_signal(link->connector_signal)) {
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@ -2150,20 +2150,20 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
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link, pipe_ctx->stream_res.stream_enc, &proposed_table);
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}
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else
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dm_logger_write(link->ctx->logger, LOG_WARNING,
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DC_LOG_WARNING(link->ctx->logger,
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"Failed to update"
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"MST allocation table for"
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"pipe idx:%d\n",
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pipe_ctx->pipe_idx);
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dm_logger_write(link->ctx->logger, LOG_MST,
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DC_LOG_MST(link->ctx->logger,
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"%s "
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"stream_count: %d: \n ",
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__func__,
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link->mst_stream_alloc_table.stream_count);
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for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
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dm_logger_write(link->ctx->logger, LOG_MST,
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DC_LOG_MST(link->ctx->logger,
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"stream_enc[%d]: 0x%x "
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"stream[%d].vcp_id: %d "
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"stream[%d].slot_count: %d\n",
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@ -2240,7 +2240,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
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link, pipe_ctx->stream_res.stream_enc, &proposed_table);
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}
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else {
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dm_logger_write(link->ctx->logger, LOG_WARNING,
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DC_LOG_WARNING(link->ctx->logger,
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"Failed to update"
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"MST allocation table for"
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"pipe idx:%d\n",
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@ -2248,14 +2248,14 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
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}
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}
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dm_logger_write(link->ctx->logger, LOG_MST,
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DC_LOG_MST(link->ctx->logger,
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"%s"
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"stream_count: %d: ",
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__func__,
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link->mst_stream_alloc_table.stream_count);
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for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
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dm_logger_write(link->ctx->logger, LOG_MST,
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DC_LOG_MST(link->ctx->logger,
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"stream_enc[%d]: 0x%x "
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"stream[%d].vcp_id: %d "
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"stream[%d].slot_count: %d\n",
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@ -2307,8 +2307,8 @@ void core_link_enable_stream(
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status = enable_link(state, pipe_ctx);
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if (status != DC_OK) {
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dm_logger_write(pipe_ctx->stream->ctx->logger,
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LOG_WARNING, "enabling link %u failed: %d\n",
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DC_LOG_WARNING(pipe_ctx->stream->ctx->logger,
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"enabling link %u failed: %d\n",
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pipe_ctx->stream->sink->link->link_index,
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status);
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@ -63,7 +63,7 @@ static void wait_for_training_aux_rd_interval(
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udelay(default_wait_in_micro_secs);
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s:\n wait = %d\n",
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__func__,
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default_wait_in_micro_secs);
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@ -79,7 +79,7 @@ static void dpcd_set_training_pattern(
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&dpcd_pattern.raw,
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1);
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s\n %x pattern = %x\n",
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__func__,
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DP_TRAINING_PATTERN_SET,
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@ -116,7 +116,7 @@ static void dpcd_set_link_settings(
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core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
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&downspread.raw, sizeof(downspread));
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
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__func__,
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DP_LINK_BW_SET,
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@ -151,7 +151,7 @@ static enum dpcd_training_patterns
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break;
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default:
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ASSERT(0);
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s: Invalid HW Training pattern: %d\n",
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__func__, pattern);
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break;
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@ -184,7 +184,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
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dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
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= dpcd_pattern.raw;
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s\n %x pattern = %x\n",
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__func__,
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DP_TRAINING_PATTERN_SET,
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@ -219,7 +219,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
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dpcd_lane,
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size_in_bytes);
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s:\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
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__func__,
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DP_TRAINING_LANE0_SET,
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@ -456,13 +456,13 @@ static void get_lane_status_and_drive_settings(
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ln_status_updated->raw = dpcd_buf[2];
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s:\n%x Lane01Status = %x\n %x Lane23Status = %x\n ",
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__func__,
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DP_LANE0_1_STATUS, dpcd_buf[0],
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DP_LANE2_3_STATUS, dpcd_buf[1]);
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s:\n %x Lane01AdjustRequest = %x\n %x Lane23AdjustRequest = %x\n",
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__func__,
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DP_ADJUST_REQUEST_LANE0_1,
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@ -556,7 +556,7 @@ static void dpcd_set_lane_settings(
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}
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*/
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dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
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DC_LOG_HW_LINK_TRAINING(link->ctx->logger,
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"%s\n %x VS set = %x PE set = %x max VS Reached = %x max PE Reached = %x\n",
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__func__,
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DP_TRAINING_LANE0_SET,
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@ -669,7 +669,7 @@ static bool perform_post_lt_adj_req_sequence(
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}
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if (!req_drv_setting_changed) {
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dm_logger_write(link->ctx->logger, LOG_WARNING,
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DC_LOG_WARNING(link->ctx->logger,
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"%s: Post Link Training Adjust Request Timed out\n",
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__func__);
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@ -677,7 +677,7 @@ static bool perform_post_lt_adj_req_sequence(
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return true;
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}
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}
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dm_logger_write(link->ctx->logger, LOG_WARNING,
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DC_LOG_WARNING(link->ctx->logger,
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"%s: Post Link Training Adjust Request limit reached\n",
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__func__);
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@ -885,7 +885,7 @@ static enum link_training_result perform_clock_recovery_sequence(
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if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
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ASSERT(0);
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dm_logger_write(link->ctx->logger, LOG_ERROR,
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DC_LOG_ERROR(link->ctx->logger,
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"%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
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__func__,
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LINK_TRAINING_MAX_CR_RETRY);
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@ -1606,7 +1606,7 @@ static bool hpd_rx_irq_check_link_loss_status(
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if (sink_status_changed ||
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!hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
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dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
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DC_LOG_HW_HPD_IRQ(link->ctx->logger,
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"%s: Link Status changed.\n", __func__);
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return_code = true;
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@ -1620,7 +1620,7 @@ static bool hpd_rx_irq_check_link_loss_status(
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sizeof(irq_reg_rx_power_state));
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if (dpcd_result != DC_OK) {
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dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
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DC_LOG_HW_HPD_IRQ(link->ctx->logger,
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"%s: DPCD read failed to obtain power state.\n",
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__func__);
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} else {
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@ -1982,7 +1982,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
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* PSR and device auto test, refer to function handle_sst_hpd_irq
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* in DAL2.1*/
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dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
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DC_LOG_HW_HPD_IRQ(link->ctx->logger,
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"%s: Got short pulse HPD on link %d\n",
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__func__, link->link_index);
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@ -1997,7 +1997,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
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*out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
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if (result != DC_OK) {
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dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
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DC_LOG_HW_HPD_IRQ(link->ctx->logger,
|
||||
"%s: DPCD read failed to obtain irq data\n",
|
||||
__func__);
|
||||
return false;
|
||||
|
@ -2016,7 +2016,7 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd
|
|||
}
|
||||
|
||||
if (!allow_hpd_rx_irq(link)) {
|
||||
dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ,
|
||||
DC_LOG_HW_HPD_IRQ(link->ctx->logger,
|
||||
"%s: skipping HPD handling on %d\n",
|
||||
__func__, link->link_index);
|
||||
return false;
|
||||
|
|
|
@ -893,7 +893,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
|
|||
/* May need to re-check lb size after this in some obscure scenario */
|
||||
calculate_inits_and_adj_vp(pipe_ctx, &recout_skip);
|
||||
|
||||
dm_logger_write(pipe_ctx->stream->ctx->logger, LOG_SCALER,
|
||||
DC_LOG_SCALER(pipe_ctx->stream->ctx->logger,
|
||||
"%s: Viewport:\nheight:%d width:%d x:%d "
|
||||
"y:%d\n dst_rect:\nheight:%d width:%d x:%d "
|
||||
"y:%d\n",
|
||||
|
|
|
@ -403,7 +403,7 @@ static bool dce_abm_set_backlight_level(
|
|||
{
|
||||
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
|
||||
|
||||
dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT,
|
||||
DC_LOG_BACKLIGHT(abm->ctx->logger,
|
||||
"New Backlight level: %d (0x%X)\n",
|
||||
backlight_level, backlight_level);
|
||||
|
||||
|
|
|
@ -63,7 +63,7 @@ static void write_indirect_azalia_reg(struct audio *audio,
|
|||
REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
|
||||
AZALIA_ENDPOINT_REG_DATA, reg_data);
|
||||
|
||||
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
|
||||
DC_LOG_HW_AUDIO(CTX->logger,
|
||||
"AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
|
||||
reg_index, reg_data);
|
||||
}
|
||||
|
@ -81,7 +81,7 @@ static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index
|
|||
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
|
||||
value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
|
||||
|
||||
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
|
||||
DC_LOG_HW_AUDIO(CTX->logger,
|
||||
"AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
|
||||
reg_index, value);
|
||||
|
||||
|
@ -364,7 +364,7 @@ void dce_aud_az_enable(struct audio *audio)
|
|||
CLOCK_GATING_DISABLE);
|
||||
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
|
||||
|
||||
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
|
||||
DC_LOG_HW_AUDIO(CTX->logger,
|
||||
"\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
|
||||
audio->inst, value);
|
||||
}
|
||||
|
@ -390,7 +390,7 @@ void dce_aud_az_disable(struct audio *audio)
|
|||
CLOCK_GATING_DISABLE);
|
||||
AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
|
||||
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
|
||||
dm_logger_write(CTX->logger, LOG_HW_AUDIO,
|
||||
DC_LOG_HW_AUDIO(CTX->logger,
|
||||
"\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
|
||||
audio->inst, value);
|
||||
}
|
||||
|
@ -795,7 +795,7 @@ void dce_aud_wall_dto_setup(
|
|||
crtc_info->calculated_pixel_clock,
|
||||
&clock_info);
|
||||
|
||||
dm_logger_write(audio->ctx->logger, LOG_HW_AUDIO,\
|
||||
DC_LOG_HW_AUDIO(audio->ctx->logger, \
|
||||
"\n%s:Input::requested_pixel_clock = %d"\
|
||||
"calculated_pixel_clock =%d\n"\
|
||||
"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
|
||||
|
|
|
@ -288,7 +288,7 @@ static uint32_t calculate_pixel_clock_pll_dividers(
|
|||
uint32_t max_ref_divider;
|
||||
|
||||
if (pll_settings->adjusted_pix_clk == 0) {
|
||||
dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(calc_pll_cs->ctx->logger,
|
||||
"%s Bad requested pixel clock", __func__);
|
||||
return MAX_PLL_CALC_ERROR;
|
||||
}
|
||||
|
@ -349,13 +349,13 @@ static uint32_t calculate_pixel_clock_pll_dividers(
|
|||
* ## SVS Wed 15 Jul 2009 */
|
||||
|
||||
if (min_post_divider > max_post_divider) {
|
||||
dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(calc_pll_cs->ctx->logger,
|
||||
"%s Post divider range is invalid", __func__);
|
||||
return MAX_PLL_CALC_ERROR;
|
||||
}
|
||||
|
||||
if (min_ref_divider > max_ref_divider) {
|
||||
dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(calc_pll_cs->ctx->logger,
|
||||
"%s Reference divider range is invalid", __func__);
|
||||
return MAX_PLL_CALC_ERROR;
|
||||
}
|
||||
|
@ -493,7 +493,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
|
|||
if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
|
||||
/* Should never happen, ASSERT and fill up values to be able
|
||||
* to continue. */
|
||||
dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(clk_src->base.ctx->logger,
|
||||
"%s: Failed to adjust pixel clock!!", __func__);
|
||||
pll_settings->actual_pix_clk =
|
||||
pix_clk_params->requested_pix_clk;
|
||||
|
@ -560,7 +560,7 @@ static uint32_t dce110_get_pix_clk_dividers(
|
|||
|
||||
if (pix_clk_params == NULL || pll_settings == NULL
|
||||
|| pix_clk_params->requested_pix_clk == 0) {
|
||||
dm_logger_write(clk_src->base.ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(clk_src->base.ctx->logger,
|
||||
"%s: Invalid parameters!!\n", __func__);
|
||||
return pll_calc_error;
|
||||
}
|
||||
|
@ -1054,12 +1054,12 @@ static void get_ss_info_from_atombios(
|
|||
uint32_t i;
|
||||
|
||||
if (ss_entries_num == NULL) {
|
||||
dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
|
||||
DC_LOG_SYNC(clk_src->base.ctx->logger,
|
||||
"Invalid entry !!!\n");
|
||||
return;
|
||||
}
|
||||
if (spread_spectrum_data == NULL) {
|
||||
dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
|
||||
DC_LOG_SYNC(clk_src->base.ctx->logger,
|
||||
"Invalid array pointer!!!\n");
|
||||
return;
|
||||
}
|
||||
|
@ -1104,7 +1104,7 @@ static void get_ss_info_from_atombios(
|
|||
++i, ++ss_info_cur, ++ss_data_cur) {
|
||||
|
||||
if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
|
||||
dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
|
||||
DC_LOG_SYNC(clk_src->base.ctx->logger,
|
||||
"Invalid ATOMBIOS SS Table!!!\n");
|
||||
goto out_free_data;
|
||||
}
|
||||
|
@ -1114,9 +1114,9 @@ static void get_ss_info_from_atombios(
|
|||
if (as_signal == AS_SIGNAL_TYPE_HDMI
|
||||
&& ss_info_cur->spread_spectrum_percentage > 6){
|
||||
/* invalid input, do nothing */
|
||||
dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
|
||||
DC_LOG_SYNC(clk_src->base.ctx->logger,
|
||||
"Invalid SS percentage ");
|
||||
dm_logger_write(clk_src->base.ctx->logger, LOG_SYNC,
|
||||
DC_LOG_SYNC(clk_src->base.ctx->logger,
|
||||
"for HDMI in ATOMBIOS info Table!!!\n");
|
||||
continue;
|
||||
}
|
||||
|
@ -1228,12 +1228,12 @@ static bool calc_pll_max_vco_construct(
|
|||
if (init_data->num_fract_fb_divider_decimal_point == 0 ||
|
||||
init_data->num_fract_fb_divider_decimal_point_precision >
|
||||
init_data->num_fract_fb_divider_decimal_point) {
|
||||
dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(calc_pll_cs->ctx->logger,
|
||||
"The dec point num or precision is incorrect!");
|
||||
return false;
|
||||
}
|
||||
if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
|
||||
dm_logger_write(calc_pll_cs->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(calc_pll_cs->ctx->logger,
|
||||
"Incorrect fract feedback divider precision num!");
|
||||
return false;
|
||||
}
|
||||
|
|
|
@ -292,7 +292,7 @@ static enum dm_pp_clocks_state dce_get_required_clocks_state(
|
|||
|
||||
low_req_clk = i + 1;
|
||||
if (low_req_clk > clk->max_clks_state) {
|
||||
dm_logger_write(clk->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(clk->ctx->logger,
|
||||
"%s: clocks unsupported disp_clk %d pix_clk %d",
|
||||
__func__,
|
||||
req_clocks->display_clk_khz,
|
||||
|
@ -312,7 +312,7 @@ static bool dce_clock_set_min_clocks_state(
|
|||
|
||||
if (clocks_state > clk->max_clks_state) {
|
||||
/*Requested state exceeds max supported state.*/
|
||||
dm_logger_write(clk->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(clk->ctx->logger,
|
||||
"Requested state exceeds max supported state");
|
||||
return false;
|
||||
} else if (clocks_state == clk->cur_min_clks_state) {
|
||||
|
|
|
@ -827,7 +827,7 @@ void dce110_link_encoder_hw_init(
|
|||
result = link_transmitter_control(enc110, &cntl);
|
||||
|
||||
if (result != BP_RESULT_OK) {
|
||||
dm_logger_write(ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(ctx->logger,
|
||||
"%s: Failed to execute VBIOS command table!\n",
|
||||
__func__);
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
@ -928,7 +928,7 @@ void dce110_link_encoder_enable_tmds_output(
|
|||
result = link_transmitter_control(enc110, &cntl);
|
||||
|
||||
if (result != BP_RESULT_OK) {
|
||||
dm_logger_write(ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(ctx->logger,
|
||||
"%s: Failed to execute VBIOS command table!\n",
|
||||
__func__);
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
@ -969,7 +969,7 @@ void dce110_link_encoder_enable_dp_output(
|
|||
result = link_transmitter_control(enc110, &cntl);
|
||||
|
||||
if (result != BP_RESULT_OK) {
|
||||
dm_logger_write(ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(ctx->logger,
|
||||
"%s: Failed to execute VBIOS command table!\n",
|
||||
__func__);
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
@ -1010,7 +1010,7 @@ void dce110_link_encoder_enable_dp_mst_output(
|
|||
result = link_transmitter_control(enc110, &cntl);
|
||||
|
||||
if (result != BP_RESULT_OK) {
|
||||
dm_logger_write(ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(ctx->logger,
|
||||
"%s: Failed to execute VBIOS command table!\n",
|
||||
__func__);
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
@ -1053,7 +1053,7 @@ void dce110_link_encoder_disable_output(
|
|||
result = link_transmitter_control(enc110, &cntl);
|
||||
|
||||
if (result != BP_RESULT_OK) {
|
||||
dm_logger_write(ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(ctx->logger,
|
||||
"%s: Failed to execute VBIOS command table!\n",
|
||||
__func__);
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
|
|
@ -277,8 +277,8 @@ static void dce110_update_hdmi_info_packet(
|
|||
#endif
|
||||
default:
|
||||
/* invalid HW packet index */
|
||||
dm_logger_write(
|
||||
ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
ctx->logger,
|
||||
"Invalid HW packet index: %s()\n",
|
||||
__func__);
|
||||
return;
|
||||
|
@ -1386,7 +1386,7 @@ static void dce110_se_setup_hdmi_audio(
|
|||
crtc_info->requested_pixel_clock,
|
||||
crtc_info->calculated_pixel_clock,
|
||||
&audio_clock_info);
|
||||
dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
|
||||
DC_LOG_HW_AUDIO(enc->ctx->logger,
|
||||
"\n%s:Input::requested_pixel_clock = %d" \
|
||||
"calculated_pixel_clock = %d \n", __func__, \
|
||||
crtc_info->requested_pixel_clock, \
|
||||
|
|
|
@ -693,7 +693,7 @@ static int dce_transform_get_max_num_of_supported_lines(
|
|||
break;
|
||||
|
||||
default:
|
||||
dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(xfm_dce->base.ctx->logger,
|
||||
"%s: Invalid LB pixel depth",
|
||||
__func__);
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
@ -791,7 +791,7 @@ static void dce_transform_set_pixel_storage_depth(
|
|||
if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
|
||||
/*we should use unsupported capabilities
|
||||
* unless it is required by w/a*/
|
||||
dm_logger_write(xfm->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(xfm->ctx->logger,
|
||||
"%s: Capability not supported",
|
||||
__func__);
|
||||
}
|
||||
|
@ -1172,7 +1172,7 @@ static void program_pwl(struct dce_transform *xfm_dce,
|
|||
}
|
||||
|
||||
if (counter == max_tries) {
|
||||
dm_logger_write(xfm_dce->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(xfm_dce->base.ctx->logger,
|
||||
"%s: regamma lut was not powered on "
|
||||
"in a timely manner,"
|
||||
" programming still proceeds\n",
|
||||
|
|
|
@ -120,13 +120,13 @@ static void wait_for_fbc_state_changed(
|
|||
}
|
||||
|
||||
if (counter == 10) {
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
cp110->base.ctx->logger,
|
||||
"%s: wait counter exceeded, changes to HW not applied",
|
||||
__func__);
|
||||
} else {
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_SYNC,
|
||||
DC_LOG_SYNC(
|
||||
cp110->base.ctx->logger,
|
||||
"FBC status changed to %d", enabled);
|
||||
}
|
||||
|
||||
|
@ -310,8 +310,8 @@ void dce110_compressor_program_compressed_surface_address_and_pitch(
|
|||
if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
|
||||
fbc_pitch = fbc_pitch / 8;
|
||||
else
|
||||
dm_logger_write(
|
||||
compressor->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
compressor->ctx->logger,
|
||||
"%s: Unexpected DCE11 compression ratio",
|
||||
__func__);
|
||||
|
||||
|
|
|
@ -816,7 +816,7 @@ void hwss_edp_wait_for_hpd_ready(
|
|||
dal_gpio_destroy_irq(&hpd);
|
||||
|
||||
if (false == edp_hpd_high) {
|
||||
dm_logger_write(ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(ctx->logger,
|
||||
"%s: wait timed out!\n", __func__);
|
||||
}
|
||||
}
|
||||
|
@ -840,7 +840,7 @@ void hwss_edp_power_control(
|
|||
if (power_up != is_panel_powered_on(hwseq)) {
|
||||
/* Send VBIOS command to prompt eDP panel power */
|
||||
|
||||
dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
|
||||
DC_LOG_HW_RESUME_S3(ctx->logger,
|
||||
"%s: Panel Power action: %s\n",
|
||||
__func__, (power_up ? "On":"Off"));
|
||||
|
||||
|
@ -856,11 +856,11 @@ void hwss_edp_power_control(
|
|||
bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
|
||||
|
||||
if (bp_result != BP_RESULT_OK)
|
||||
dm_logger_write(ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(ctx->logger,
|
||||
"%s: Panel Power bp_result: %d\n",
|
||||
__func__, bp_result);
|
||||
} else {
|
||||
dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
|
||||
DC_LOG_HW_RESUME_S3(ctx->logger,
|
||||
"%s: Skipping Panel Power action: %s\n",
|
||||
__func__, (power_up ? "On":"Off"));
|
||||
}
|
||||
|
@ -886,7 +886,7 @@ void hwss_edp_backlight_control(
|
|||
}
|
||||
|
||||
if (enable && is_panel_backlight_on(hws)) {
|
||||
dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
|
||||
DC_LOG_HW_RESUME_S3(ctx->logger,
|
||||
"%s: panel already powered up. Do nothing.\n",
|
||||
__func__);
|
||||
return;
|
||||
|
@ -894,7 +894,7 @@ void hwss_edp_backlight_control(
|
|||
|
||||
/* Send VBIOS command to control eDP panel backlight */
|
||||
|
||||
dm_logger_write(ctx->logger, LOG_HW_RESUME_S3,
|
||||
DC_LOG_HW_RESUME_S3(ctx->logger,
|
||||
"%s: backlight action: %s\n",
|
||||
__func__, (enable ? "On":"Off"));
|
||||
|
||||
|
@ -2762,7 +2762,7 @@ static void dce110_program_front_end_for_pipe(
|
|||
if (pipe_ctx->plane_state->update_flags.bits.full_update)
|
||||
dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
|
||||
|
||||
dm_logger_write(dc->ctx->logger, LOG_SURFACE,
|
||||
DC_LOG_SURFACE(dc->ctx->logger,
|
||||
"Pipe:%d 0x%x: addr hi:0x%x, "
|
||||
"addr low:0x%x, "
|
||||
"src: %d, %d, %d,"
|
||||
|
@ -2785,7 +2785,7 @@ static void dce110_program_front_end_for_pipe(
|
|||
pipe_ctx->plane_state->clip_rect.width,
|
||||
pipe_ctx->plane_state->clip_rect.height);
|
||||
|
||||
dm_logger_write(dc->ctx->logger, LOG_SURFACE,
|
||||
DC_LOG_SURFACE(dc->ctx->logger,
|
||||
"Pipe %d: width, height, x, y\n"
|
||||
"viewport:%d, %d, %d, %d\n"
|
||||
"recout: %d, %d, %d, %d\n",
|
||||
|
|
|
@ -771,8 +771,8 @@ static bool dce110_validate_bandwidth(
|
|||
{
|
||||
bool result = false;
|
||||
|
||||
dm_logger_write(
|
||||
dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(
|
||||
dc->ctx->logger,
|
||||
"%s: start",
|
||||
__func__);
|
||||
|
||||
|
@ -786,7 +786,7 @@ static bool dce110_validate_bandwidth(
|
|||
result = true;
|
||||
|
||||
if (!result)
|
||||
dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
|
||||
DC_LOG_BANDWIDTH_VALIDATION(dc->ctx->logger,
|
||||
"%s: %dx%d@%d Bandwidth validation failed!\n",
|
||||
__func__,
|
||||
context->streams[0]->timing.h_addressable,
|
||||
|
|
|
@ -606,7 +606,7 @@ static uint32_t dce110_timing_generator_v_get_vblank_counter(struct timing_gener
|
|||
static bool dce110_timing_generator_v_did_triggered_reset_occur(
|
||||
struct timing_generator *tg)
|
||||
{
|
||||
dm_logger_write(tg->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(tg->ctx->logger,
|
||||
"Timing Sync not supported on underlay pipe\n");
|
||||
return false;
|
||||
}
|
||||
|
@ -615,7 +615,7 @@ static void dce110_timing_generator_v_setup_global_swap_lock(
|
|||
struct timing_generator *tg,
|
||||
const struct dcp_gsl_params *gsl_params)
|
||||
{
|
||||
dm_logger_write(tg->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(tg->ctx->logger,
|
||||
"Timing Sync not supported on underlay pipe\n");
|
||||
return;
|
||||
}
|
||||
|
@ -624,7 +624,7 @@ static void dce110_timing_generator_v_enable_reset_trigger(
|
|||
struct timing_generator *tg,
|
||||
int source_tg_inst)
|
||||
{
|
||||
dm_logger_write(tg->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(tg->ctx->logger,
|
||||
"Timing Sync not supported on underlay pipe\n");
|
||||
return;
|
||||
}
|
||||
|
@ -632,7 +632,7 @@ static void dce110_timing_generator_v_enable_reset_trigger(
|
|||
static void dce110_timing_generator_v_disable_reset_trigger(
|
||||
struct timing_generator *tg)
|
||||
{
|
||||
dm_logger_write(tg->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(tg->ctx->logger,
|
||||
"Timing Sync not supported on underlay pipe\n");
|
||||
return;
|
||||
}
|
||||
|
@ -640,7 +640,7 @@ static void dce110_timing_generator_v_disable_reset_trigger(
|
|||
static void dce110_timing_generator_v_tear_down_global_swap_lock(
|
||||
struct timing_generator *tg)
|
||||
{
|
||||
dm_logger_write(tg->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(tg->ctx->logger,
|
||||
"Timing Sync not supported on underlay pipe\n");
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -670,7 +670,7 @@ static void dce110_xfmv_set_pixel_storage_depth(
|
|||
if (!(xfm_dce->lb_pixel_depth_supported & depth)) {
|
||||
/*we should use unsupported capabilities
|
||||
* unless it is required by w/a*/
|
||||
dm_logger_write(xfm->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(xfm->ctx->logger,
|
||||
"%s: Capability not supported",
|
||||
__func__);
|
||||
}
|
||||
|
|
|
@ -129,8 +129,8 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
|
|||
LOW_POWER_TILING_NUM_PIPES);
|
||||
break;
|
||||
default:
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
cp110->base.ctx->logger,
|
||||
"%s: Invalid LPT NUM_PIPES!!!",
|
||||
__func__);
|
||||
break;
|
||||
|
@ -175,8 +175,8 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
|
|||
LOW_POWER_TILING_NUM_BANKS);
|
||||
break;
|
||||
default:
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
cp110->base.ctx->logger,
|
||||
"%s: Invalid LPT NUM_BANKS!!!",
|
||||
__func__);
|
||||
break;
|
||||
|
@ -209,8 +209,8 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
|
|||
LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
|
||||
break;
|
||||
default:
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
cp110->base.ctx->logger,
|
||||
"%s: Invalid LPT INTERLEAVE_SIZE!!!",
|
||||
__func__);
|
||||
break;
|
||||
|
@ -253,15 +253,15 @@ static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
|
|||
LOW_POWER_TILING_ROW_SIZE);
|
||||
break;
|
||||
default:
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
cp110->base.ctx->logger,
|
||||
"%s: Invalid LPT ROW_SIZE!!!",
|
||||
__func__);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
cp110->base.ctx->logger,
|
||||
"%s: LPT MC Configuration is not provided",
|
||||
__func__);
|
||||
}
|
||||
|
@ -311,8 +311,8 @@ static void wait_for_fbc_state_changed(
|
|||
}
|
||||
|
||||
if (counter == 10) {
|
||||
dm_logger_write(
|
||||
cp110->base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
cp110->base.ctx->logger,
|
||||
"%s: wait counter exceeded, changes to HW not applied",
|
||||
__func__);
|
||||
}
|
||||
|
@ -525,8 +525,8 @@ void dce112_compressor_program_compressed_surface_address_and_pitch(
|
|||
if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
|
||||
fbc_pitch = fbc_pitch / 8;
|
||||
else
|
||||
dm_logger_write(
|
||||
compressor->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
compressor->ctx->logger,
|
||||
"%s: Unexpected DCE11 compression ratio",
|
||||
__func__);
|
||||
|
||||
|
@ -690,8 +690,8 @@ void dce112_compressor_program_lpt_control(
|
|||
LOW_POWER_TILING_MODE);
|
||||
break;
|
||||
default:
|
||||
dm_logger_write(
|
||||
compressor->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
compressor->ctx->logger,
|
||||
"%s: Invalid selected DRAM channels for LPT!!!",
|
||||
__func__);
|
||||
break;
|
||||
|
|
|
@ -722,8 +722,8 @@ bool dce112_validate_bandwidth(
|
|||
{
|
||||
bool result = false;
|
||||
|
||||
dm_logger_write(
|
||||
dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(
|
||||
dc->ctx->logger,
|
||||
"%s: start",
|
||||
__func__);
|
||||
|
||||
|
@ -737,7 +737,7 @@ bool dce112_validate_bandwidth(
|
|||
result = true;
|
||||
|
||||
if (!result)
|
||||
dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
|
||||
DC_LOG_BANDWIDTH_VALIDATION(dc->ctx->logger,
|
||||
"%s: Bandwidth validation failed!",
|
||||
__func__);
|
||||
|
||||
|
|
|
@ -147,7 +147,7 @@ bool hubbub1_verify_allow_pstate_change_high(
|
|||
if (debug_data & (1 << 30)) {
|
||||
|
||||
if (i > pstate_wait_expected_timeout_us)
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(hubbub->ctx->logger,
|
||||
"pstate took longer than expected ~%dus\n",
|
||||
i);
|
||||
|
||||
|
@ -167,7 +167,7 @@ bool hubbub1_verify_allow_pstate_change_high(
|
|||
DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1);
|
||||
forced_pstate_allow = true;
|
||||
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(hubbub->ctx->logger,
|
||||
"pstate TEST_DEBUG_DATA: 0x%X\n",
|
||||
debug_data);
|
||||
|
||||
|
@ -211,7 +211,7 @@ void hubbub1_program_watermarks(
|
|||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
|
||||
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"URGENCY_WATERMARK_A calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->a.urgent_ns, prog_wm_value);
|
||||
|
@ -219,7 +219,7 @@ void hubbub1_program_watermarks(
|
|||
prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->a.pte_meta_urgent_ns, prog_wm_value);
|
||||
|
@ -229,7 +229,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
||||
|
@ -239,7 +239,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->a.cstate_pstate.cstate_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_EXIT_WATERMARK_A calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
||||
|
@ -249,7 +249,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->a.cstate_pstate.pstate_change_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
|
||||
"HW register value = 0x%x\n\n",
|
||||
watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
|
||||
|
@ -259,7 +259,7 @@ void hubbub1_program_watermarks(
|
|||
prog_wm_value = convert_and_clamp(
|
||||
watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"URGENCY_WATERMARK_B calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->b.urgent_ns, prog_wm_value);
|
||||
|
@ -269,7 +269,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->b.pte_meta_urgent_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->b.pte_meta_urgent_ns, prog_wm_value);
|
||||
|
@ -280,7 +280,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_ENTER_WATERMARK_B calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
||||
|
@ -290,7 +290,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->b.cstate_pstate.cstate_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_EXIT_WATERMARK_B calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
||||
|
@ -300,7 +300,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->b.cstate_pstate.pstate_change_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
|
||||
|
@ -309,7 +309,7 @@ void hubbub1_program_watermarks(
|
|||
prog_wm_value = convert_and_clamp(
|
||||
watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"URGENCY_WATERMARK_C calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->c.urgent_ns, prog_wm_value);
|
||||
|
@ -319,7 +319,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->c.pte_meta_urgent_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->c.pte_meta_urgent_ns, prog_wm_value);
|
||||
|
@ -330,7 +330,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_ENTER_WATERMARK_C calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
||||
|
@ -340,7 +340,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->c.cstate_pstate.cstate_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_EXIT_WATERMARK_C calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
||||
|
@ -350,7 +350,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->c.cstate_pstate.pstate_change_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
|
||||
|
@ -359,7 +359,7 @@ void hubbub1_program_watermarks(
|
|||
prog_wm_value = convert_and_clamp(
|
||||
watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"URGENCY_WATERMARK_D calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->d.urgent_ns, prog_wm_value);
|
||||
|
@ -368,7 +368,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->d.pte_meta_urgent_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->d.pte_meta_urgent_ns, prog_wm_value);
|
||||
|
@ -379,7 +379,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_ENTER_WATERMARK_D calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
|
||||
|
@ -389,7 +389,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->d.cstate_pstate.cstate_exit_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"SR_EXIT_WATERMARK_D calculated =%d\n"
|
||||
"HW register value = 0x%x\n",
|
||||
watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
|
||||
|
@ -400,7 +400,7 @@ void hubbub1_program_watermarks(
|
|||
watermarks->d.cstate_pstate.pstate_change_ns,
|
||||
refclk_mhz, 0x1fffff);
|
||||
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
|
||||
dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(hubbub->ctx->logger,
|
||||
"DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
|
||||
"HW register value = 0x%x\n\n",
|
||||
watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
|
||||
|
|
|
@ -335,7 +335,7 @@ static void power_on_plane(
|
|||
hubp_pg_control(hws, plane_id, true);
|
||||
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
||||
IP_REQUEST_EN, 0);
|
||||
dm_logger_write(hws->ctx->logger, LOG_DEBUG,
|
||||
DC_LOG_DEBUG(hws->ctx->logger,
|
||||
"Un-gated front end for pipe %d\n", plane_id);
|
||||
}
|
||||
}
|
||||
|
@ -572,7 +572,7 @@ static void reset_back_end_for_pipe(
|
|||
return;
|
||||
|
||||
pipe_ctx->stream = NULL;
|
||||
dm_logger_write(dc->ctx->logger, LOG_DEBUG,
|
||||
DC_LOG_DEBUG(dc->ctx->logger,
|
||||
"Reset back end for pipe %d, tg:%d\n",
|
||||
pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
|
||||
}
|
||||
|
@ -632,7 +632,7 @@ static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
|
|||
dpp->funcs->dpp_reset(dpp);
|
||||
REG_SET(DC_IP_REQUEST_CNTL, 0,
|
||||
IP_REQUEST_EN, 0);
|
||||
dm_logger_write(dc->ctx->logger, LOG_DEBUG,
|
||||
DC_LOG_DEBUG(dc->ctx->logger,
|
||||
"Power gated front end %d\n", pipe_ctx->pipe_idx);
|
||||
}
|
||||
}
|
||||
|
@ -679,7 +679,7 @@ static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
|
|||
|
||||
apply_DEGVIDCN10_253_wa(dc);
|
||||
|
||||
dm_logger_write(dc->ctx->logger, LOG_DC,
|
||||
DC_LOG_DC(dc->ctx->logger,
|
||||
"Power down front end %d\n",
|
||||
pipe_ctx->pipe_idx);
|
||||
}
|
||||
|
@ -1102,7 +1102,7 @@ static void dcn10_enable_per_frame_crtc_position_reset(
|
|||
struct dc *core_dc,
|
||||
struct pipe_ctx *pipe_ctx)
|
||||
{
|
||||
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
|
||||
"\n============== DML TTU Output parameters [%d] ==============\n"
|
||||
"qos_level_low_wm: %d, \n"
|
||||
"qos_level_high_wm: %d, \n"
|
||||
|
@ -1132,7 +1132,7 @@ static void dcn10_enable_per_frame_crtc_position_reset(
|
|||
pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
|
||||
);
|
||||
|
||||
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
|
||||
"\n============== DML DLG Output parameters [%d] ==============\n"
|
||||
"refcyc_h_blank_end: %d, \n"
|
||||
"dlg_vblank_end: %d, \n"
|
||||
|
@ -1167,7 +1167,7 @@ static void dcn10_enable_per_frame_crtc_position_reset(
|
|||
pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
|
||||
);
|
||||
|
||||
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
|
||||
"\ndst_y_per_meta_row_nom_l: %d, \n"
|
||||
"refcyc_per_meta_chunk_nom_l: %d, \n"
|
||||
"refcyc_per_line_delivery_pre_l: %d, \n"
|
||||
|
@ -1197,7 +1197,7 @@ static void dcn10_enable_per_frame_crtc_position_reset(
|
|||
pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
|
||||
);
|
||||
|
||||
dm_logger_write(core_dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
|
||||
"\n============== DML RQ Output parameters [%d] ==============\n"
|
||||
"chunk_size: %d \n"
|
||||
"min_chunk_size: %d \n"
|
||||
|
@ -1330,7 +1330,7 @@ static void dcn10_enable_plane(
|
|||
|
||||
/* TODO: enable/disable in dm as per update type.
|
||||
if (plane_state) {
|
||||
dm_logger_write(dc->ctx->logger, LOG_DC,
|
||||
DC_LOG_DC(dc->ctx->logger,
|
||||
"Pipe:%d 0x%x: addr hi:0x%x, "
|
||||
"addr low:0x%x, "
|
||||
"src: %d, %d, %d,"
|
||||
|
@ -1348,7 +1348,7 @@ static void dcn10_enable_plane(
|
|||
plane_state->dst_rect.width,
|
||||
plane_state->dst_rect.height);
|
||||
|
||||
dm_logger_write(dc->ctx->logger, LOG_DC,
|
||||
DC_LOG_DC(dc->ctx->logger,
|
||||
"Pipe %d: width, height, x, y format:%d\n"
|
||||
"viewport:%d, %d, %d, %d\n"
|
||||
"recout: %d, %d, %d, %d\n",
|
||||
|
@ -1959,7 +1959,7 @@ static void dcn10_apply_ctx_for_surface(
|
|||
plane_atomic_disconnect(dc, old_pipe_ctx);
|
||||
removed_pipe[i] = true;
|
||||
|
||||
dm_logger_write(dc->ctx->logger, LOG_DC,
|
||||
DC_LOG_DC(dc->ctx->logger,
|
||||
"Reset mpcc for pipe %d\n",
|
||||
old_pipe_ctx->pipe_idx);
|
||||
}
|
||||
|
@ -2002,7 +2002,7 @@ static void dcn10_apply_ctx_for_surface(
|
|||
dcn10_verify_allow_pstate_change_high(dc);
|
||||
}
|
||||
}
|
||||
/* dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
/* DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
|
||||
"\n============== Watermark parameters ==============\n"
|
||||
"a.urgent_ns: %d \n"
|
||||
"a.cstate_enter_plus_exit: %d \n"
|
||||
|
@ -2025,7 +2025,7 @@ static void dcn10_apply_ctx_for_surface(
|
|||
context->bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns,
|
||||
context->bw.dcn.watermarks.b.pte_meta_urgent_ns
|
||||
);
|
||||
dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
|
||||
DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
|
||||
"\nc.urgent_ns: %d \n"
|
||||
"c.cstate_enter_plus_exit: %d \n"
|
||||
"c.cstate_exit: %d \n"
|
||||
|
@ -2268,7 +2268,7 @@ static void dcn10_wait_for_mpcc_disconnect(
|
|||
res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
|
||||
pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
|
||||
hubp->funcs->set_blank(hubp, true);
|
||||
/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
|
||||
/*DC_LOG_ERROR(dc->ctx->logger,
|
||||
"[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
|
||||
i);*/
|
||||
}
|
||||
|
|
|
@ -274,7 +274,7 @@ static bool read_command(
|
|||
|
||||
if (request->payload.address_space ==
|
||||
I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
|
||||
dm_logger_write(engine->base.ctx->logger, LOG_I2C_AUX, "READ: addr:0x%x value:0x%x Result:%d",
|
||||
DC_LOG_I2C_AUX(engine->base.ctx->logger, "READ: addr:0x%x value:0x%x Result:%d",
|
||||
request->payload.address,
|
||||
request->payload.data[0],
|
||||
ctx.operation_succeeded);
|
||||
|
@ -483,7 +483,7 @@ static bool write_command(
|
|||
|
||||
if (request->payload.address_space ==
|
||||
I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
|
||||
dm_logger_write(engine->base.ctx->logger, LOG_I2C_AUX, "WRITE: addr:0x%x value:0x%x Result:%d",
|
||||
DC_LOG_I2C_AUX(engine->base.ctx->logger, "WRITE: addr:0x%x value:0x%x Result:%d",
|
||||
request->payload.address,
|
||||
request->payload.data[0],
|
||||
ctx.operation_succeeded);
|
||||
|
|
|
@ -525,8 +525,8 @@ static void construct(
|
|||
REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
|
||||
|
||||
if (xtal_ref_div == 0) {
|
||||
dm_logger_write(
|
||||
hw_engine->base.base.base.ctx->logger, LOG_WARNING,
|
||||
DC_LOG_WARNING(
|
||||
hw_engine->base.base.base.ctx->logger,
|
||||
"Invalid base timer divider\n",
|
||||
__func__);
|
||||
xtal_ref_div = 2;
|
||||
|
|
|
@ -181,8 +181,8 @@ bool dal_irq_service_dummy_set(
|
|||
const struct irq_source_info *info,
|
||||
bool enable)
|
||||
{
|
||||
dm_logger_write(
|
||||
irq_service->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(
|
||||
irq_service->ctx->logger,
|
||||
"%s: called for non-implemented irq source\n",
|
||||
__func__);
|
||||
return false;
|
||||
|
@ -192,8 +192,8 @@ bool dal_irq_service_dummy_ack(
|
|||
struct irq_service *irq_service,
|
||||
const struct irq_source_info *info)
|
||||
{
|
||||
dm_logger_write(
|
||||
irq_service->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(
|
||||
irq_service->ctx->logger,
|
||||
"%s: called for non-implemented irq source\n",
|
||||
__func__);
|
||||
return false;
|
||||
|
|
|
@ -104,8 +104,8 @@ bool dal_irq_service_set(
|
|||
find_irq_source_info(irq_service, source);
|
||||
|
||||
if (!info) {
|
||||
dm_logger_write(
|
||||
irq_service->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(
|
||||
irq_service->ctx->logger,
|
||||
"%s: cannot find irq info table entry for %d\n",
|
||||
__func__,
|
||||
source);
|
||||
|
@ -142,8 +142,8 @@ bool dal_irq_service_ack(
|
|||
find_irq_source_info(irq_service, source);
|
||||
|
||||
if (!info) {
|
||||
dm_logger_write(
|
||||
irq_service->ctx->logger, LOG_ERROR,
|
||||
DC_LOG_ERROR(
|
||||
irq_service->ctx->logger,
|
||||
"%s: cannot find irq info table entry for %d\n",
|
||||
__func__,
|
||||
source);
|
||||
|
|
|
@ -29,6 +29,39 @@
|
|||
#include "os_types.h"
|
||||
|
||||
#define MAX_NAME_LEN 32
|
||||
#define DC_LOG_ERROR(a, b, ...) dm_logger_write(a, LOG_ERROR, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_WARNING(a, b, ...) dm_logger_write(a, LOG_WARNING, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_DEBUG(a, b, ...) dm_logger_write(a, LOG_DEBUG, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_DC(a, b, ...) dm_logger_write(a, LOG_DC, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_DTN(a, b, ...) dm_logger_write(a, LOG_DTN, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_SURFACE(a, b, ...) dm_logger_write(a, LOG_SURFACE, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_HW_HOTPLUG(a, b, ...) dm_logger_write(a, LOG_HW_HOTPLUG, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_HW_LINK_TRAINING(a, b, ...) dm_logger_write(a, LOG_HW_LINK_TRAINING, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_HW_SET_MODE(a, b, ...) dm_logger_write(a, LOG_HW_SET_MODE, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_HW_RESUME_S3(a, b, ...) dm_logger_write(a, LOG_HW_RESUME_S3, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_HW_AUDIO(a, b, ...) dm_logger_write(a, LOG_HW_AUDIO, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_HW_HPD_IRQ(a, b, ...) dm_logger_write(a, LOG_HW_HPD_IRQ, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_MST(a, b, ...) dm_logger_write(a, LOG_MST, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_SCALER(a, b, ...) dm_logger_write(a, LOG_SCALER, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_BIOS(a, b, ...) dm_logger_write(a, LOG_BIOS, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_BANDWIDTH_CALCS(a, b, ...) dm_logger_write(a, LOG_BANDWIDTH_CALCS, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_BANDWIDTH_VALIDATION(a, b, ...) dm_logger_write(a, LOG_BANDWIDTH_VALIDATION, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_I2C_AUX(a, b, ...) dm_logger_write(a, LOG_I2C_AUX, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_SYNC(a, b, ...) dm_logger_write(a, LOG_SYNC, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_BACKLIGHT(a, b, ...) dm_logger_write(a, LOG_BACKLIGHT, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_FEATURE_OVERRIDE(a, b, ...) dm_logger_write(a, LOG_FEATURE_OVERRIDE, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_DETECTION_EDID_PARSER(a, b, ...) dm_logger_write(a, LOG_DETECTION_EDID_PARSER, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_DETECTION_DP_CAPS(a, b, ...) dm_logger_write(a, LOG_DETECTION_DP_CAPS, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_RESOURCE(a, b, ...) dm_logger_write(a, LOG_RESOURCE, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_DML(a, b, ...) dm_logger_write(a, LOG_DML, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_EVENT_MODE_SET(a, b, ...) dm_logger_write(a, LOG_EVENT_MODE_SET, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_EVENT_DETECTION(a, b, ...) dm_logger_write(a, LOG_EVENT_DETECTION, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_EVENT_LINK_TRAINING(a, b, ...) dm_logger_write(a, LOG_EVENT_LINK_TRAINING, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_EVENT_LINK_LOSS(a, b, ...) dm_logger_write(a, LOG_EVENT_LINK_LOSS, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_EVENT_UNDERFLOW(a, b, ...) dm_logger_write(a, LOG_EVENT_UNDERFLOW, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_IF_TRACE(a, b, ...) dm_logger_write(a, LOG_IF_TRACE, b, ## __VA_ARGS__)
|
||||
#define DC_LOG_PERF_TRACE(a, b, ...) dm_logger_write(a, LOG_PERF_TRACE, b, ## __VA_ARGS__)
|
||||
|
||||
|
||||
struct dal_logger;
|
||||
|
||||
|
|
Loading…
Reference in New Issue