Merge remote-tracking branches 'asoc/topic/fsl', 'asoc/topic/fsl-ssi', 'asoc/topic/fsl_asrc' and 'asoc/topic/hdac_hdmi' into asoc-next
This commit is contained in:
Mark Brown
commit
2f1eceda4d
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@ -169,6 +169,10 @@ struct snd_pcm_ops {
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#define SNDRV_PCM_FMTBIT_IMA_ADPCM _SNDRV_PCM_FMTBIT(IMA_ADPCM)
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#define SNDRV_PCM_FMTBIT_MPEG _SNDRV_PCM_FMTBIT(MPEG)
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#define SNDRV_PCM_FMTBIT_GSM _SNDRV_PCM_FMTBIT(GSM)
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#define SNDRV_PCM_FMTBIT_S20_LE _SNDRV_PCM_FMTBIT(S20_LE)
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#define SNDRV_PCM_FMTBIT_U20_LE _SNDRV_PCM_FMTBIT(U20_LE)
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#define SNDRV_PCM_FMTBIT_S20_BE _SNDRV_PCM_FMTBIT(S20_BE)
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#define SNDRV_PCM_FMTBIT_U20_BE _SNDRV_PCM_FMTBIT(U20_BE)
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#define SNDRV_PCM_FMTBIT_SPECIAL _SNDRV_PCM_FMTBIT(SPECIAL)
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#define SNDRV_PCM_FMTBIT_S24_3LE _SNDRV_PCM_FMTBIT(S24_3LE)
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#define SNDRV_PCM_FMTBIT_U24_3LE _SNDRV_PCM_FMTBIT(U24_3LE)
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@ -202,6 +206,8 @@ struct snd_pcm_ops {
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#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_LE
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#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_LE
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#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
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#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_LE
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#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_LE
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#endif
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#ifdef SNDRV_BIG_ENDIAN
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#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_BE
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@ -213,6 +219,8 @@ struct snd_pcm_ops {
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#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_BE
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#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_BE
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#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE
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#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_BE
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#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_BE
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#endif
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struct snd_pcm_file {
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@ -102,6 +102,8 @@ struct snd_compr_stream;
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SNDRV_PCM_FMTBIT_S16_BE |\
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SNDRV_PCM_FMTBIT_S20_3LE |\
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SNDRV_PCM_FMTBIT_S20_3BE |\
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SNDRV_PCM_FMTBIT_S20_LE |\
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SNDRV_PCM_FMTBIT_S20_BE |\
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SNDRV_PCM_FMTBIT_S24_3LE |\
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SNDRV_PCM_FMTBIT_S24_3BE |\
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SNDRV_PCM_FMTBIT_S32_LE |\
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@ -214,6 +214,11 @@ typedef int __bitwise snd_pcm_format_t;
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#define SNDRV_PCM_FORMAT_IMA_ADPCM ((__force snd_pcm_format_t) 22)
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#define SNDRV_PCM_FORMAT_MPEG ((__force snd_pcm_format_t) 23)
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#define SNDRV_PCM_FORMAT_GSM ((__force snd_pcm_format_t) 24)
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#define SNDRV_PCM_FORMAT_S20_LE ((__force snd_pcm_format_t) 25) /* in four bytes, LSB justified */
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#define SNDRV_PCM_FORMAT_S20_BE ((__force snd_pcm_format_t) 26) /* in four bytes, LSB justified */
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#define SNDRV_PCM_FORMAT_U20_LE ((__force snd_pcm_format_t) 27) /* in four bytes, LSB justified */
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#define SNDRV_PCM_FORMAT_U20_BE ((__force snd_pcm_format_t) 28) /* in four bytes, LSB justified */
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/* gap in the numbering for a future standard linear format */
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#define SNDRV_PCM_FORMAT_SPECIAL ((__force snd_pcm_format_t) 31)
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#define SNDRV_PCM_FORMAT_S24_3LE ((__force snd_pcm_format_t) 32) /* in three bytes */
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#define SNDRV_PCM_FORMAT_S24_3BE ((__force snd_pcm_format_t) 33) /* in three bytes */
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@ -248,6 +253,8 @@ typedef int __bitwise snd_pcm_format_t;
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#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_LE
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#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_LE
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#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE
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#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_LE
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#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_LE
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#endif
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#ifdef SNDRV_BIG_ENDIAN
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#define SNDRV_PCM_FORMAT_S16 SNDRV_PCM_FORMAT_S16_BE
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@ -259,6 +266,8 @@ typedef int __bitwise snd_pcm_format_t;
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#define SNDRV_PCM_FORMAT_FLOAT SNDRV_PCM_FORMAT_FLOAT_BE
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#define SNDRV_PCM_FORMAT_FLOAT64 SNDRV_PCM_FORMAT_FLOAT64_BE
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#define SNDRV_PCM_FORMAT_IEC958_SUBFRAME SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE
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#define SNDRV_PCM_FORMAT_S20 SNDRV_PCM_FORMAT_S20_BE
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#define SNDRV_PCM_FORMAT_U20 SNDRV_PCM_FORMAT_U20_BE
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#endif
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typedef int __bitwise snd_pcm_subformat_t;
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@ -163,13 +163,30 @@ static struct pcm_format_data pcm_formats[(INT)SNDRV_PCM_FORMAT_LAST+1] = {
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.width = 32, .phys = 32, .le = 0, .signd = 0,
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.silence = { 0x69, 0x69, 0x69, 0x69 },
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},
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/* FIXME: the following three formats are not defined properly yet */
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/* FIXME: the following two formats are not defined properly yet */
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[SNDRV_PCM_FORMAT_MPEG] = {
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.le = -1, .signd = -1,
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},
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[SNDRV_PCM_FORMAT_GSM] = {
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.le = -1, .signd = -1,
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},
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[SNDRV_PCM_FORMAT_S20_LE] = {
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.width = 20, .phys = 32, .le = 1, .signd = 1,
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.silence = {},
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},
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[SNDRV_PCM_FORMAT_S20_BE] = {
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.width = 20, .phys = 32, .le = 0, .signd = 1,
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.silence = {},
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},
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[SNDRV_PCM_FORMAT_U20_LE] = {
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.width = 20, .phys = 32, .le = 1, .signd = 0,
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.silence = { 0x00, 0x00, 0x08, 0x00 },
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},
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[SNDRV_PCM_FORMAT_U20_BE] = {
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.width = 20, .phys = 32, .le = 0, .signd = 0,
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.silence = { 0x00, 0x08, 0x00, 0x00 },
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},
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/* FIXME: the following format is not defined properly yet */
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[SNDRV_PCM_FORMAT_SPECIAL] = {
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.le = -1, .signd = -1,
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},
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@ -2186,6 +2186,8 @@ static const struct hda_device_id hdmi_list[] = {
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HDA_CODEC_EXT_ENTRY(0x80862809, 0x100000, "Skylake HDMI", 0),
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HDA_CODEC_EXT_ENTRY(0x8086280a, 0x100000, "Broxton HDMI", 0),
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HDA_CODEC_EXT_ENTRY(0x8086280b, 0x100000, "Kabylake HDMI", 0),
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HDA_CODEC_EXT_ENTRY(0x8086280c, 0x100000, "Cannonlake HDMI",
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&intel_glk_drv_data),
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HDA_CODEC_EXT_ENTRY(0x8086280d, 0x100000, "Geminilake HDMI",
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&intel_glk_drv_data),
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{}
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@ -442,8 +442,8 @@ static int fsl_asoc_card_late_probe(struct snd_soc_card *card)
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if (fsl_asoc_card_is_ac97(priv)) {
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#if IS_ENABLED(CONFIG_SND_AC97_CODEC)
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struct snd_soc_codec *codec = rtd->codec;
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struct snd_ac97 *ac97 = snd_soc_codec_get_drvdata(codec);
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struct snd_soc_component *component = rtd->codec_dai->component;
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struct snd_ac97 *ac97 = snd_soc_component_get_drvdata(component);
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/*
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* Use slots 3/4 for S/PDIF so SSI won't try to enable
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@ -57,7 +57,7 @@
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#define REG_ASRDOC 0x74
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#define REG_ASRDI(i) (REG_ASRDIA + (i << 3))
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#define REG_ASRDO(i) (REG_ASRDOA + (i << 3))
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#define REG_ASRDx(x, i) (x == IN ? REG_ASRDI(i) : REG_ASRDO(i))
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#define REG_ASRDx(x, i) ((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
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#define REG_ASRIDRHA 0x80
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#define REG_ASRIDRLA 0x84
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File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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/*
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* fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 SoC
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* fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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@ -12,198 +12,261 @@
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#ifndef _MPC8610_I2S_H
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#define _MPC8610_I2S_H
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/* SSI registers */
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#define CCSR_SSI_STX0 0x00
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#define CCSR_SSI_STX1 0x04
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#define CCSR_SSI_SRX0 0x08
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#define CCSR_SSI_SRX1 0x0c
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#define CCSR_SSI_SCR 0x10
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#define CCSR_SSI_SISR 0x14
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#define CCSR_SSI_SIER 0x18
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#define CCSR_SSI_STCR 0x1c
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#define CCSR_SSI_SRCR 0x20
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#define CCSR_SSI_STCCR 0x24
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#define CCSR_SSI_SRCCR 0x28
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#define CCSR_SSI_SFCSR 0x2c
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#define CCSR_SSI_STR 0x30
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#define CCSR_SSI_SOR 0x34
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#define CCSR_SSI_SACNT 0x38
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#define CCSR_SSI_SACADD 0x3c
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#define CCSR_SSI_SACDAT 0x40
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#define CCSR_SSI_SATAG 0x44
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#define CCSR_SSI_STMSK 0x48
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#define CCSR_SSI_SRMSK 0x4c
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#define CCSR_SSI_SACCST 0x50
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#define CCSR_SSI_SACCEN 0x54
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#define CCSR_SSI_SACCDIS 0x58
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#define RX 0
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#define TX 1
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#define CCSR_SSI_SCR_SYNC_TX_FS 0x00001000
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#define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800
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#define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400
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#define CCSR_SSI_SCR_TCH_EN 0x00000100
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#define CCSR_SSI_SCR_SYS_CLK_EN 0x00000080
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#define CCSR_SSI_SCR_I2S_MODE_MASK 0x00000060
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#define CCSR_SSI_SCR_I2S_MODE_NORMAL 0x00000000
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#define CCSR_SSI_SCR_I2S_MODE_MASTER 0x00000020
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#define CCSR_SSI_SCR_I2S_MODE_SLAVE 0x00000040
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#define CCSR_SSI_SCR_SYN 0x00000010
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#define CCSR_SSI_SCR_NET 0x00000008
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#define CCSR_SSI_SCR_RE 0x00000004
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#define CCSR_SSI_SCR_TE 0x00000002
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#define CCSR_SSI_SCR_SSIEN 0x00000001
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/* -- SSI Register Map -- */
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#define CCSR_SSI_SISR_RFRC 0x01000000
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#define CCSR_SSI_SISR_TFRC 0x00800000
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#define CCSR_SSI_SISR_CMDAU 0x00040000
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#define CCSR_SSI_SISR_CMDDU 0x00020000
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#define CCSR_SSI_SISR_RXT 0x00010000
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#define CCSR_SSI_SISR_RDR1 0x00008000
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#define CCSR_SSI_SISR_RDR0 0x00004000
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#define CCSR_SSI_SISR_TDE1 0x00002000
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#define CCSR_SSI_SISR_TDE0 0x00001000
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#define CCSR_SSI_SISR_ROE1 0x00000800
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#define CCSR_SSI_SISR_ROE0 0x00000400
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#define CCSR_SSI_SISR_TUE1 0x00000200
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#define CCSR_SSI_SISR_TUE0 0x00000100
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#define CCSR_SSI_SISR_TFS 0x00000080
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#define CCSR_SSI_SISR_RFS 0x00000040
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#define CCSR_SSI_SISR_TLS 0x00000020
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#define CCSR_SSI_SISR_RLS 0x00000010
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#define CCSR_SSI_SISR_RFF1 0x00000008
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#define CCSR_SSI_SISR_RFF0 0x00000004
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#define CCSR_SSI_SISR_TFE1 0x00000002
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#define CCSR_SSI_SISR_TFE0 0x00000001
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/* SSI Transmit Data Register 0 */
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#define REG_SSI_STX0 0x00
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/* SSI Transmit Data Register 1 */
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#define REG_SSI_STX1 0x04
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/* SSI Receive Data Register 0 */
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#define REG_SSI_SRX0 0x08
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/* SSI Receive Data Register 1 */
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#define REG_SSI_SRX1 0x0c
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/* SSI Control Register */
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#define REG_SSI_SCR 0x10
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/* SSI Interrupt Status Register */
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#define REG_SSI_SISR 0x14
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/* SSI Interrupt Enable Register */
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#define REG_SSI_SIER 0x18
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/* SSI Transmit Configuration Register */
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#define REG_SSI_STCR 0x1c
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/* SSI Receive Configuration Register */
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#define REG_SSI_SRCR 0x20
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#define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR)
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/* SSI Transmit Clock Control Register */
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#define REG_SSI_STCCR 0x24
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/* SSI Receive Clock Control Register */
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#define REG_SSI_SRCCR 0x28
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#define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR)
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/* SSI FIFO Control/Status Register */
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#define REG_SSI_SFCSR 0x2c
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/*
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* SSI Test Register (Intended for debugging purposes only)
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*
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* Note: STR is not documented in recent IMX datasheet, but
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* is described in IMX51 reference manual at section 56.3.3.14
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*/
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#define REG_SSI_STR 0x30
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/*
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* SSI Option Register (Intended for internal use only)
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*
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* Note: SOR is not documented in recent IMX datasheet, but
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* is described in IMX51 reference manual at section 56.3.3.15
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*/
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#define REG_SSI_SOR 0x34
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/* SSI AC97 Control Register */
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#define REG_SSI_SACNT 0x38
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/* SSI AC97 Command Address Register */
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#define REG_SSI_SACADD 0x3c
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/* SSI AC97 Command Data Register */
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#define REG_SSI_SACDAT 0x40
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/* SSI AC97 Tag Register */
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#define REG_SSI_SATAG 0x44
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/* SSI Transmit Time Slot Mask Register */
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#define REG_SSI_STMSK 0x48
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/* SSI Receive Time Slot Mask Register */
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#define REG_SSI_SRMSK 0x4c
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#define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK)
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/*
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* SSI AC97 Channel Status Register
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*
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* The status could be changed by:
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* 1) Writing a '1' bit at some position in SACCEN sets relevant bit in SACCST
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* 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit
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* 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link
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*/
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#define REG_SSI_SACCST 0x50
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/* SSI AC97 Channel Enable Register -- Set bits in SACCST */
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#define REG_SSI_SACCEN 0x54
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/* SSI AC97 Channel Disable Register -- Clear bits in SACCST */
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#define REG_SSI_SACCDIS 0x58
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#define CCSR_SSI_SIER_RFRC_EN 0x01000000
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#define CCSR_SSI_SIER_TFRC_EN 0x00800000
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#define CCSR_SSI_SIER_RDMAE 0x00400000
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#define CCSR_SSI_SIER_RIE 0x00200000
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#define CCSR_SSI_SIER_TDMAE 0x00100000
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#define CCSR_SSI_SIER_TIE 0x00080000
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#define CCSR_SSI_SIER_CMDAU_EN 0x00040000
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#define CCSR_SSI_SIER_CMDDU_EN 0x00020000
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#define CCSR_SSI_SIER_RXT_EN 0x00010000
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#define CCSR_SSI_SIER_RDR1_EN 0x00008000
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#define CCSR_SSI_SIER_RDR0_EN 0x00004000
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#define CCSR_SSI_SIER_TDE1_EN 0x00002000
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#define CCSR_SSI_SIER_TDE0_EN 0x00001000
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#define CCSR_SSI_SIER_ROE1_EN 0x00000800
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#define CCSR_SSI_SIER_ROE0_EN 0x00000400
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#define CCSR_SSI_SIER_TUE1_EN 0x00000200
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#define CCSR_SSI_SIER_TUE0_EN 0x00000100
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#define CCSR_SSI_SIER_TFS_EN 0x00000080
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#define CCSR_SSI_SIER_RFS_EN 0x00000040
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#define CCSR_SSI_SIER_TLS_EN 0x00000020
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#define CCSR_SSI_SIER_RLS_EN 0x00000010
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#define CCSR_SSI_SIER_RFF1_EN 0x00000008
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#define CCSR_SSI_SIER_RFF0_EN 0x00000004
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#define CCSR_SSI_SIER_TFE1_EN 0x00000002
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#define CCSR_SSI_SIER_TFE0_EN 0x00000001
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/* -- SSI Register Field Maps -- */
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#define CCSR_SSI_STCR_TXBIT0 0x00000200
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#define CCSR_SSI_STCR_TFEN1 0x00000100
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#define CCSR_SSI_STCR_TFEN0 0x00000080
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#define CCSR_SSI_STCR_TFDIR 0x00000040
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#define CCSR_SSI_STCR_TXDIR 0x00000020
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#define CCSR_SSI_STCR_TSHFD 0x00000010
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#define CCSR_SSI_STCR_TSCKP 0x00000008
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#define CCSR_SSI_STCR_TFSI 0x00000004
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#define CCSR_SSI_STCR_TFSL 0x00000002
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#define CCSR_SSI_STCR_TEFS 0x00000001
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/* SSI Control Register -- REG_SSI_SCR 0x10 */
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#define SSI_SCR_SYNC_TX_FS 0x00001000
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#define SSI_SCR_RFR_CLK_DIS 0x00000800
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#define SSI_SCR_TFR_CLK_DIS 0x00000400
|
||||
#define SSI_SCR_TCH_EN 0x00000100
|
||||
#define SSI_SCR_SYS_CLK_EN 0x00000080
|
||||
#define SSI_SCR_I2S_MODE_MASK 0x00000060
|
||||
#define SSI_SCR_I2S_MODE_NORMAL 0x00000000
|
||||
#define SSI_SCR_I2S_MODE_MASTER 0x00000020
|
||||
#define SSI_SCR_I2S_MODE_SLAVE 0x00000040
|
||||
#define SSI_SCR_SYN 0x00000010
|
||||
#define SSI_SCR_NET 0x00000008
|
||||
#define SSI_SCR_I2S_NET_MASK (SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK)
|
||||
#define SSI_SCR_RE 0x00000004
|
||||
#define SSI_SCR_TE 0x00000002
|
||||
#define SSI_SCR_SSIEN 0x00000001
|
||||
|
||||
#define CCSR_SSI_SRCR_RXEXT 0x00000400
|
||||
#define CCSR_SSI_SRCR_RXBIT0 0x00000200
|
||||
#define CCSR_SSI_SRCR_RFEN1 0x00000100
|
||||
#define CCSR_SSI_SRCR_RFEN0 0x00000080
|
||||
#define CCSR_SSI_SRCR_RFDIR 0x00000040
|
||||
#define CCSR_SSI_SRCR_RXDIR 0x00000020
|
||||
#define CCSR_SSI_SRCR_RSHFD 0x00000010
|
||||
#define CCSR_SSI_SRCR_RSCKP 0x00000008
|
||||
#define CCSR_SSI_SRCR_RFSI 0x00000004
|
||||
#define CCSR_SSI_SRCR_RFSL 0x00000002
|
||||
#define CCSR_SSI_SRCR_REFS 0x00000001
|
||||
/* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */
|
||||
#define SSI_SISR_RFRC 0x01000000
|
||||
#define SSI_SISR_TFRC 0x00800000
|
||||
#define SSI_SISR_CMDAU 0x00040000
|
||||
#define SSI_SISR_CMDDU 0x00020000
|
||||
#define SSI_SISR_RXT 0x00010000
|
||||
#define SSI_SISR_RDR1 0x00008000
|
||||
#define SSI_SISR_RDR0 0x00004000
|
||||
#define SSI_SISR_TDE1 0x00002000
|
||||
#define SSI_SISR_TDE0 0x00001000
|
||||
#define SSI_SISR_ROE1 0x00000800
|
||||
#define SSI_SISR_ROE0 0x00000400
|
||||
#define SSI_SISR_TUE1 0x00000200
|
||||
#define SSI_SISR_TUE0 0x00000100
|
||||
#define SSI_SISR_TFS 0x00000080
|
||||
#define SSI_SISR_RFS 0x00000040
|
||||
#define SSI_SISR_TLS 0x00000020
|
||||
#define SSI_SISR_RLS 0x00000010
|
||||
#define SSI_SISR_RFF1 0x00000008
|
||||
#define SSI_SISR_RFF0 0x00000004
|
||||
#define SSI_SISR_TFE1 0x00000002
|
||||
#define SSI_SISR_TFE0 0x00000001
|
||||
|
||||
/* STCCR and SRCCR */
|
||||
#define CCSR_SSI_SxCCR_DIV2_SHIFT 18
|
||||
#define CCSR_SSI_SxCCR_DIV2 0x00040000
|
||||
#define CCSR_SSI_SxCCR_PSR_SHIFT 17
|
||||
#define CCSR_SSI_SxCCR_PSR 0x00020000
|
||||
#define CCSR_SSI_SxCCR_WL_SHIFT 13
|
||||
#define CCSR_SSI_SxCCR_WL_MASK 0x0001E000
|
||||
#define CCSR_SSI_SxCCR_WL(x) \
|
||||
(((((x) / 2) - 1) << CCSR_SSI_SxCCR_WL_SHIFT) & CCSR_SSI_SxCCR_WL_MASK)
|
||||
#define CCSR_SSI_SxCCR_DC_SHIFT 8
|
||||
#define CCSR_SSI_SxCCR_DC_MASK 0x00001F00
|
||||
#define CCSR_SSI_SxCCR_DC(x) \
|
||||
((((x) - 1) << CCSR_SSI_SxCCR_DC_SHIFT) & CCSR_SSI_SxCCR_DC_MASK)
|
||||
#define CCSR_SSI_SxCCR_PM_SHIFT 0
|
||||
#define CCSR_SSI_SxCCR_PM_MASK 0x000000FF
|
||||
#define CCSR_SSI_SxCCR_PM(x) \
|
||||
((((x) - 1) << CCSR_SSI_SxCCR_PM_SHIFT) & CCSR_SSI_SxCCR_PM_MASK)
|
||||
/* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */
|
||||
#define SSI_SIER_RFRC_EN 0x01000000
|
||||
#define SSI_SIER_TFRC_EN 0x00800000
|
||||
#define SSI_SIER_RDMAE 0x00400000
|
||||
#define SSI_SIER_RIE 0x00200000
|
||||
#define SSI_SIER_TDMAE 0x00100000
|
||||
#define SSI_SIER_TIE 0x00080000
|
||||
#define SSI_SIER_CMDAU_EN 0x00040000
|
||||
#define SSI_SIER_CMDDU_EN 0x00020000
|
||||
#define SSI_SIER_RXT_EN 0x00010000
|
||||
#define SSI_SIER_RDR1_EN 0x00008000
|
||||
#define SSI_SIER_RDR0_EN 0x00004000
|
||||
#define SSI_SIER_TDE1_EN 0x00002000
|
||||
#define SSI_SIER_TDE0_EN 0x00001000
|
||||
#define SSI_SIER_ROE1_EN 0x00000800
|
||||
#define SSI_SIER_ROE0_EN 0x00000400
|
||||
#define SSI_SIER_TUE1_EN 0x00000200
|
||||
#define SSI_SIER_TUE0_EN 0x00000100
|
||||
#define SSI_SIER_TFS_EN 0x00000080
|
||||
#define SSI_SIER_RFS_EN 0x00000040
|
||||
#define SSI_SIER_TLS_EN 0x00000020
|
||||
#define SSI_SIER_RLS_EN 0x00000010
|
||||
#define SSI_SIER_RFF1_EN 0x00000008
|
||||
#define SSI_SIER_RFF0_EN 0x00000004
|
||||
#define SSI_SIER_TFE1_EN 0x00000002
|
||||
#define SSI_SIER_TFE0_EN 0x00000001
|
||||
|
||||
/* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */
|
||||
#define SSI_STCR_TXBIT0 0x00000200
|
||||
#define SSI_STCR_TFEN1 0x00000100
|
||||
#define SSI_STCR_TFEN0 0x00000080
|
||||
#define SSI_STCR_TFDIR 0x00000040
|
||||
#define SSI_STCR_TXDIR 0x00000020
|
||||
#define SSI_STCR_TSHFD 0x00000010
|
||||
#define SSI_STCR_TSCKP 0x00000008
|
||||
#define SSI_STCR_TFSI 0x00000004
|
||||
#define SSI_STCR_TFSL 0x00000002
|
||||
#define SSI_STCR_TEFS 0x00000001
|
||||
|
||||
/* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */
|
||||
#define SSI_SRCR_RXEXT 0x00000400
|
||||
#define SSI_SRCR_RXBIT0 0x00000200
|
||||
#define SSI_SRCR_RFEN1 0x00000100
|
||||
#define SSI_SRCR_RFEN0 0x00000080
|
||||
#define SSI_SRCR_RFDIR 0x00000040
|
||||
#define SSI_SRCR_RXDIR 0x00000020
|
||||
#define SSI_SRCR_RSHFD 0x00000010
|
||||
#define SSI_SRCR_RSCKP 0x00000008
|
||||
#define SSI_SRCR_RFSI 0x00000004
|
||||
#define SSI_SRCR_RFSL 0x00000002
|
||||
#define SSI_SRCR_REFS 0x00000001
|
||||
|
||||
/*
|
||||
* The xFCNT bits are read-only, and the xFWM bits are read/write. Use the
|
||||
* CCSR_SSI_SFCSR_xFCNTy() macros to read the FIFO counters, and use the
|
||||
* CCSR_SSI_SFCSR_xFWMy() macros to set the watermarks.
|
||||
* SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24
|
||||
* SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28
|
||||
*/
|
||||
#define CCSR_SSI_SFCSR_RFCNT1_SHIFT 28
|
||||
#define CCSR_SSI_SFCSR_RFCNT1_MASK 0xF0000000
|
||||
#define CCSR_SSI_SFCSR_RFCNT1(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_RFCNT1_MASK) >> CCSR_SSI_SFCSR_RFCNT1_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_TFCNT1_SHIFT 24
|
||||
#define CCSR_SSI_SFCSR_TFCNT1_MASK 0x0F000000
|
||||
#define CCSR_SSI_SFCSR_TFCNT1(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_TFCNT1_MASK) >> CCSR_SSI_SFCSR_TFCNT1_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_RFWM1_SHIFT 20
|
||||
#define CCSR_SSI_SFCSR_RFWM1_MASK 0x00F00000
|
||||
#define CCSR_SSI_SFCSR_RFWM1(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_RFWM1_SHIFT) & CCSR_SSI_SFCSR_RFWM1_MASK)
|
||||
#define CCSR_SSI_SFCSR_TFWM1_SHIFT 16
|
||||
#define CCSR_SSI_SFCSR_TFWM1_MASK 0x000F0000
|
||||
#define CCSR_SSI_SFCSR_TFWM1(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_TFWM1_SHIFT) & CCSR_SSI_SFCSR_TFWM1_MASK)
|
||||
#define CCSR_SSI_SFCSR_RFCNT0_SHIFT 12
|
||||
#define CCSR_SSI_SFCSR_RFCNT0_MASK 0x0000F000
|
||||
#define CCSR_SSI_SFCSR_RFCNT0(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_RFCNT0_MASK) >> CCSR_SSI_SFCSR_RFCNT0_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_TFCNT0_SHIFT 8
|
||||
#define CCSR_SSI_SFCSR_TFCNT0_MASK 0x00000F00
|
||||
#define CCSR_SSI_SFCSR_TFCNT0(x) \
|
||||
(((x) & CCSR_SSI_SFCSR_TFCNT0_MASK) >> CCSR_SSI_SFCSR_TFCNT0_SHIFT)
|
||||
#define CCSR_SSI_SFCSR_RFWM0_SHIFT 4
|
||||
#define CCSR_SSI_SFCSR_RFWM0_MASK 0x000000F0
|
||||
#define CCSR_SSI_SFCSR_RFWM0(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_RFWM0_SHIFT) & CCSR_SSI_SFCSR_RFWM0_MASK)
|
||||
#define CCSR_SSI_SFCSR_TFWM0_SHIFT 0
|
||||
#define CCSR_SSI_SFCSR_TFWM0_MASK 0x0000000F
|
||||
#define CCSR_SSI_SFCSR_TFWM0(x) \
|
||||
(((x) << CCSR_SSI_SFCSR_TFWM0_SHIFT) & CCSR_SSI_SFCSR_TFWM0_MASK)
|
||||
#define SSI_SxCCR_DIV2_SHIFT 18
|
||||
#define SSI_SxCCR_DIV2 0x00040000
|
||||
#define SSI_SxCCR_PSR_SHIFT 17
|
||||
#define SSI_SxCCR_PSR 0x00020000
|
||||
#define SSI_SxCCR_WL_SHIFT 13
|
||||
#define SSI_SxCCR_WL_MASK 0x0001E000
|
||||
#define SSI_SxCCR_WL(x) \
|
||||
(((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK)
|
||||
#define SSI_SxCCR_DC_SHIFT 8
|
||||
#define SSI_SxCCR_DC_MASK 0x00001F00
|
||||
#define SSI_SxCCR_DC(x) \
|
||||
((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK)
|
||||
#define SSI_SxCCR_PM_SHIFT 0
|
||||
#define SSI_SxCCR_PM_MASK 0x000000FF
|
||||
#define SSI_SxCCR_PM(x) \
|
||||
((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK)
|
||||
|
||||
#define CCSR_SSI_STR_TEST 0x00008000
|
||||
#define CCSR_SSI_STR_RCK2TCK 0x00004000
|
||||
#define CCSR_SSI_STR_RFS2TFS 0x00002000
|
||||
#define CCSR_SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
|
||||
#define CCSR_SSI_STR_TXD2RXD 0x00000080
|
||||
#define CCSR_SSI_STR_TCK2RCK 0x00000040
|
||||
#define CCSR_SSI_STR_TFS2RFS 0x00000020
|
||||
#define CCSR_SSI_STR_TXSTATE(x) ((x) & 0x1F)
|
||||
/*
|
||||
* SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c
|
||||
*
|
||||
* Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only
|
||||
* Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write
|
||||
*/
|
||||
#define SSI_SFCSR_RFCNT1_SHIFT 28
|
||||
#define SSI_SFCSR_RFCNT1_MASK 0xF0000000
|
||||
#define SSI_SFCSR_RFCNT1(x) \
|
||||
(((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT)
|
||||
#define SSI_SFCSR_TFCNT1_SHIFT 24
|
||||
#define SSI_SFCSR_TFCNT1_MASK 0x0F000000
|
||||
#define SSI_SFCSR_TFCNT1(x) \
|
||||
(((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT)
|
||||
#define SSI_SFCSR_RFWM1_SHIFT 20
|
||||
#define SSI_SFCSR_RFWM1_MASK 0x00F00000
|
||||
#define SSI_SFCSR_RFWM1(x) \
|
||||
(((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK)
|
||||
#define SSI_SFCSR_TFWM1_SHIFT 16
|
||||
#define SSI_SFCSR_TFWM1_MASK 0x000F0000
|
||||
#define SSI_SFCSR_TFWM1(x) \
|
||||
(((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK)
|
||||
#define SSI_SFCSR_RFCNT0_SHIFT 12
|
||||
#define SSI_SFCSR_RFCNT0_MASK 0x0000F000
|
||||
#define SSI_SFCSR_RFCNT0(x) \
|
||||
(((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT)
|
||||
#define SSI_SFCSR_TFCNT0_SHIFT 8
|
||||
#define SSI_SFCSR_TFCNT0_MASK 0x00000F00
|
||||
#define SSI_SFCSR_TFCNT0(x) \
|
||||
(((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT)
|
||||
#define SSI_SFCSR_RFWM0_SHIFT 4
|
||||
#define SSI_SFCSR_RFWM0_MASK 0x000000F0
|
||||
#define SSI_SFCSR_RFWM0(x) \
|
||||
(((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK)
|
||||
#define SSI_SFCSR_TFWM0_SHIFT 0
|
||||
#define SSI_SFCSR_TFWM0_MASK 0x0000000F
|
||||
#define SSI_SFCSR_TFWM0(x) \
|
||||
(((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK)
|
||||
|
||||
#define CCSR_SSI_SOR_CLKOFF 0x00000040
|
||||
#define CCSR_SSI_SOR_RX_CLR 0x00000020
|
||||
#define CCSR_SSI_SOR_TX_CLR 0x00000010
|
||||
#define CCSR_SSI_SOR_INIT 0x00000008
|
||||
#define CCSR_SSI_SOR_WAIT_SHIFT 1
|
||||
#define CCSR_SSI_SOR_WAIT_MASK 0x00000006
|
||||
#define CCSR_SSI_SOR_WAIT(x) (((x) & 3) << CCSR_SSI_SOR_WAIT_SHIFT)
|
||||
#define CCSR_SSI_SOR_SYNRST 0x00000001
|
||||
/* SSI Test Register -- REG_SSI_STR 0x30 */
|
||||
#define SSI_STR_TEST 0x00008000
|
||||
#define SSI_STR_RCK2TCK 0x00004000
|
||||
#define SSI_STR_RFS2TFS 0x00002000
|
||||
#define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
|
||||
#define SSI_STR_TXD2RXD 0x00000080
|
||||
#define SSI_STR_TCK2RCK 0x00000040
|
||||
#define SSI_STR_TFS2RFS 0x00000020
|
||||
#define SSI_STR_TXSTATE(x) ((x) & 0x1F)
|
||||
|
||||
#define CCSR_SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
|
||||
#define CCSR_SSI_SACNT_WR 0x00000010
|
||||
#define CCSR_SSI_SACNT_RD 0x00000008
|
||||
#define CCSR_SSI_SACNT_RDWR_MASK 0x00000018
|
||||
#define CCSR_SSI_SACNT_TIF 0x00000004
|
||||
#define CCSR_SSI_SACNT_FV 0x00000002
|
||||
#define CCSR_SSI_SACNT_AC97EN 0x00000001
|
||||
/* SSI Option Register -- REG_SSI_SOR 0x34 */
|
||||
#define SSI_SOR_CLKOFF 0x00000040
|
||||
#define SSI_SOR_RX_CLR 0x00000020
|
||||
#define SSI_SOR_TX_CLR 0x00000010
|
||||
#define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR)
|
||||
#define SSI_SOR_INIT 0x00000008
|
||||
#define SSI_SOR_WAIT_SHIFT 1
|
||||
#define SSI_SOR_WAIT_MASK 0x00000006
|
||||
#define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT)
|
||||
#define SSI_SOR_SYNRST 0x00000001
|
||||
|
||||
/* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */
|
||||
#define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
|
||||
#define SSI_SACNT_WR 0x00000010
|
||||
#define SSI_SACNT_RD 0x00000008
|
||||
#define SSI_SACNT_RDWR_MASK 0x00000018
|
||||
#define SSI_SACNT_TIF 0x00000004
|
||||
#define SSI_SACNT_FV 0x00000002
|
||||
#define SSI_SACNT_AC97EN 0x00000001
|
||||
|
||||
|
||||
struct device;
|
||||
|
|
@ -255,7 +318,7 @@ static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
|
|||
}
|
||||
|
||||
static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
|
||||
struct device *dev)
|
||||
struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,86 +18,86 @@
|
|||
|
||||
void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr)
|
||||
{
|
||||
if (sisr & CCSR_SSI_SISR_RFRC)
|
||||
if (sisr & SSI_SISR_RFRC)
|
||||
dbg->stats.rfrc++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TFRC)
|
||||
if (sisr & SSI_SISR_TFRC)
|
||||
dbg->stats.tfrc++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_CMDAU)
|
||||
if (sisr & SSI_SISR_CMDAU)
|
||||
dbg->stats.cmdau++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_CMDDU)
|
||||
if (sisr & SSI_SISR_CMDDU)
|
||||
dbg->stats.cmddu++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_RXT)
|
||||
if (sisr & SSI_SISR_RXT)
|
||||
dbg->stats.rxt++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_RDR1)
|
||||
if (sisr & SSI_SISR_RDR1)
|
||||
dbg->stats.rdr1++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_RDR0)
|
||||
if (sisr & SSI_SISR_RDR0)
|
||||
dbg->stats.rdr0++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TDE1)
|
||||
if (sisr & SSI_SISR_TDE1)
|
||||
dbg->stats.tde1++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TDE0)
|
||||
if (sisr & SSI_SISR_TDE0)
|
||||
dbg->stats.tde0++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_ROE1)
|
||||
if (sisr & SSI_SISR_ROE1)
|
||||
dbg->stats.roe1++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_ROE0)
|
||||
if (sisr & SSI_SISR_ROE0)
|
||||
dbg->stats.roe0++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TUE1)
|
||||
if (sisr & SSI_SISR_TUE1)
|
||||
dbg->stats.tue1++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TUE0)
|
||||
if (sisr & SSI_SISR_TUE0)
|
||||
dbg->stats.tue0++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TFS)
|
||||
if (sisr & SSI_SISR_TFS)
|
||||
dbg->stats.tfs++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_RFS)
|
||||
if (sisr & SSI_SISR_RFS)
|
||||
dbg->stats.rfs++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TLS)
|
||||
if (sisr & SSI_SISR_TLS)
|
||||
dbg->stats.tls++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_RLS)
|
||||
if (sisr & SSI_SISR_RLS)
|
||||
dbg->stats.rls++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_RFF1)
|
||||
if (sisr & SSI_SISR_RFF1)
|
||||
dbg->stats.rff1++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_RFF0)
|
||||
if (sisr & SSI_SISR_RFF0)
|
||||
dbg->stats.rff0++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TFE1)
|
||||
if (sisr & SSI_SISR_TFE1)
|
||||
dbg->stats.tfe1++;
|
||||
|
||||
if (sisr & CCSR_SSI_SISR_TFE0)
|
||||
if (sisr & SSI_SISR_TFE0)
|
||||
dbg->stats.tfe0++;
|
||||
}
|
||||
|
||||
/* Show the statistics of a flag only if its interrupt is enabled. The
|
||||
* compiler will optimze this code to a no-op if the interrupt is not
|
||||
* enabled.
|
||||
/**
|
||||
* Show the statistics of a flag only if its interrupt is enabled
|
||||
*
|
||||
* Compilers will optimize it to a no-op if the interrupt is disabled
|
||||
*/
|
||||
#define SIER_SHOW(flag, name) \
|
||||
do { \
|
||||
if (CCSR_SSI_SIER_##flag) \
|
||||
if (SSI_SIER_##flag) \
|
||||
seq_printf(s, #name "=%u\n", ssi_dbg->stats.name); \
|
||||
} while (0)
|
||||
|
||||
|
||||
/**
|
||||
* fsl_sysfs_ssi_show: display SSI statistics
|
||||
* Display the statistics for the current SSI device
|
||||
*
|
||||
* Display the statistics for the current SSI device. To avoid confusion,
|
||||
* we only show those counts that are enabled.
|
||||
* To avoid confusion, only show those counts that are enabled
|
||||
*/
|
||||
static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
|
||||
{
|
||||
|
|
@ -147,7 +147,8 @@ int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev)
|
|||
return -ENOMEM;
|
||||
|
||||
ssi_dbg->dbg_stats = debugfs_create_file("stats", S_IRUGO,
|
||||
ssi_dbg->dbg_dir, ssi_dbg, &fsl_ssi_stats_ops);
|
||||
ssi_dbg->dbg_dir, ssi_dbg,
|
||||
&fsl_ssi_stats_ops);
|
||||
if (!ssi_dbg->dbg_stats) {
|
||||
debugfs_remove(ssi_dbg->dbg_dir);
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
Loading…
Reference in New Issue