locking/atomic, arch/arm64: Implement atomic{,64}_fetch_{add,sub,and,andnot,or,xor}{,_relaxed,_acquire,_release}() for LSE instructions
Implement FETCH-OP atomic primitives, these are very similar to the existing OP-RETURN primitives we already have, except they return the value of the atomic variable _before_ modification. This is especially useful for irreversible operations -- such as bitops (because it becomes impossible to reconstruct the state prior to modification). This patch implements the LSE variants. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Steve Capper <steve.capper@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arch@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: http://lkml.kernel.org/r/1461344493-8262-2-git-send-email-will.deacon@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Will Deacon
Ingo Molnar
parent
6822a84dd4
commit
2efe95fe69
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@ -46,6 +46,38 @@ ATOMIC_OP(add, stadd)
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#undef ATOMIC_OP
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#define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \
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static inline int atomic_fetch_##op##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC(fetch_##op##name), \
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/* LSE atomics */ \
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" " #asm_op #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return w0; \
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}
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#define ATOMIC_FETCH_OPS(op, asm_op) \
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ATOMIC_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC_FETCH_OPS(andnot, ldclr)
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ATOMIC_FETCH_OPS(or, ldset)
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ATOMIC_FETCH_OPS(xor, ldeor)
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ATOMIC_FETCH_OPS(add, ldadd)
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_FETCH_OPS
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#define ATOMIC_OP_ADD_RETURN(name, mb, cl...) \
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static inline int atomic_add_return##name(int i, atomic_t *v) \
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{ \
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@ -90,6 +122,33 @@ static inline void atomic_and(int i, atomic_t *v)
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: __LL_SC_CLOBBERS);
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}
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#define ATOMIC_FETCH_OP_AND(name, mb, cl...) \
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static inline int atomic_fetch_and##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC(fetch_and##name), \
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/* LSE atomics */ \
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" mvn %w[i], %w[i]\n" \
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" ldclr" #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return w0; \
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}
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ATOMIC_FETCH_OP_AND(_relaxed, )
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ATOMIC_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC_FETCH_OP_AND(_release, l, "memory")
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ATOMIC_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC_FETCH_OP_AND
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static inline void atomic_sub(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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@ -135,6 +194,33 @@ ATOMIC_OP_SUB_RETURN(_release, l, "memory")
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ATOMIC_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC_OP_SUB_RETURN
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#define ATOMIC_FETCH_OP_SUB(name, mb, cl...) \
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static inline int atomic_fetch_sub##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC(fetch_sub##name), \
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/* LSE atomics */ \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return w0; \
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}
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ATOMIC_FETCH_OP_SUB(_relaxed, )
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ATOMIC_FETCH_OP_SUB(_acquire, a, "memory")
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ATOMIC_FETCH_OP_SUB(_release, l, "memory")
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ATOMIC_FETCH_OP_SUB( , al, "memory")
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#undef ATOMIC_FETCH_OP_SUB
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#undef __LL_SC_ATOMIC
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#define __LL_SC_ATOMIC64(op) __LL_SC_CALL(atomic64_##op)
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@ -158,6 +244,38 @@ ATOMIC64_OP(add, stadd)
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#undef ATOMIC64_OP
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#define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \
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static inline long atomic64_fetch_##op##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC64(fetch_##op##name), \
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/* LSE atomics */ \
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" " #asm_op #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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#define ATOMIC64_FETCH_OPS(op, asm_op) \
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ATOMIC64_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC64_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC64_FETCH_OPS(andnot, ldclr)
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ATOMIC64_FETCH_OPS(or, ldset)
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ATOMIC64_FETCH_OPS(xor, ldeor)
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ATOMIC64_FETCH_OPS(add, ldadd)
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_FETCH_OPS
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#define ATOMIC64_OP_ADD_RETURN(name, mb, cl...) \
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static inline long atomic64_add_return##name(long i, atomic64_t *v) \
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{ \
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@ -202,6 +320,33 @@ static inline void atomic64_and(long i, atomic64_t *v)
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: __LL_SC_CLOBBERS);
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}
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#define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \
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static inline long atomic64_fetch_and##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("w0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC64(fetch_and##name), \
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/* LSE atomics */ \
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" mvn %[i], %[i]\n" \
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" ldclr" #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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ATOMIC64_FETCH_OP_AND(_relaxed, )
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ATOMIC64_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC64_FETCH_OP_AND(_release, l, "memory")
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ATOMIC64_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC64_FETCH_OP_AND
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static inline void atomic64_sub(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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@ -248,6 +393,33 @@ ATOMIC64_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC64_OP_SUB_RETURN
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#define ATOMIC64_FETCH_OP_SUB(name, mb, cl...) \
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static inline long atomic64_fetch_sub##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("w0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" nop\n" \
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__LL_SC_ATOMIC64(fetch_sub##name), \
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/* LSE atomics */ \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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ATOMIC64_FETCH_OP_SUB(_relaxed, )
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ATOMIC64_FETCH_OP_SUB(_acquire, a, "memory")
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ATOMIC64_FETCH_OP_SUB(_release, l, "memory")
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ATOMIC64_FETCH_OP_SUB( , al, "memory")
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#undef ATOMIC64_FETCH_OP_SUB
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static inline long atomic64_dec_if_positive(atomic64_t *v)
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{
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register long x0 asm ("x0") = (long)v;
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