clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to the CPU clock tree with a supplementaty mux to select the CPU0 clock instead. Leave this as read-only since it's set up by the early boot stages. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Neil Armstrong
Jerome Brunet
parent
3dd02b7334
commit
2edccd319f
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@ -676,6 +676,172 @@ static struct clk_regmap g12b_cpub_clk = {
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},
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};
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static struct clk_regmap sm1_gp1_pll;
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/* Datasheet names this field as "premux0" */
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static struct clk_regmap sm1_dsu_clk_premux0 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x3,
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.shift = 0,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_dyn0_sel",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "xtal", },
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{ .hw = &g12a_fclk_div2.hw },
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{ .hw = &g12a_fclk_div3.hw },
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{ .hw = &sm1_gp1_pll.hw },
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},
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.num_parents = 4,
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},
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};
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/* Datasheet names this field as "premux1" */
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static struct clk_regmap sm1_dsu_clk_premux1 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x3,
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.shift = 16,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_dyn1_sel",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "xtal", },
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{ .hw = &g12a_fclk_div2.hw },
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{ .hw = &g12a_fclk_div3.hw },
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{ .hw = &sm1_gp1_pll.hw },
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},
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.num_parents = 4,
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},
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};
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/* Datasheet names this field as "Mux0_divn_tcnt" */
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static struct clk_regmap sm1_dsu_clk_mux0_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.shift = 4,
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.width = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_dyn0_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&sm1_dsu_clk_premux0.hw
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},
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.num_parents = 1,
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},
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};
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/* Datasheet names this field as "postmux0" */
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static struct clk_regmap sm1_dsu_clk_postmux0 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 2,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_dyn0",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&sm1_dsu_clk_premux0.hw,
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&sm1_dsu_clk_mux0_div.hw,
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},
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.num_parents = 2,
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},
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};
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/* Datasheet names this field as "Mux1_divn_tcnt" */
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static struct clk_regmap sm1_dsu_clk_mux1_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.shift = 20,
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.width = 6,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_dyn1_div",
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.ops = &clk_regmap_divider_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&sm1_dsu_clk_premux1.hw
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},
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.num_parents = 1,
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},
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};
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/* Datasheet names this field as "postmux1" */
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static struct clk_regmap sm1_dsu_clk_postmux1 = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 18,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_dyn1",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&sm1_dsu_clk_premux1.hw,
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&sm1_dsu_clk_mux1_div.hw,
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},
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.num_parents = 2,
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},
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};
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/* Datasheet names this field as "Final_dyn_mux_sel" */
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static struct clk_regmap sm1_dsu_clk_dyn = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 10,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_dyn",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&sm1_dsu_clk_postmux0.hw,
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&sm1_dsu_clk_postmux1.hw,
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},
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.num_parents = 2,
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},
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};
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/* Datasheet names this field as "Final_mux_sel" */
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static struct clk_regmap sm1_dsu_final_clk = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL5,
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.mask = 0x1,
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.shift = 11,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk_final",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&sm1_dsu_clk_dyn.hw,
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&g12a_sys_pll.hw,
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},
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.num_parents = 2,
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},
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};
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/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
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static struct clk_regmap sm1_dsu_clk = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_SYS_CPU_CLK_CNTL6,
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.mask = 0x1,
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.shift = 27,
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},
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.hw.init = &(struct clk_init_data){
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.name = "dsu_clk",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&g12a_cpu_clk.hw,
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&sm1_dsu_final_clk.hw,
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},
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.num_parents = 2,
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},
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};
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static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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@ -4401,6 +4567,15 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
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[CLKID_TS] = &g12a_ts.hw,
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[CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
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[CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
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[CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
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[CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
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[CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
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[CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
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[CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
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[CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
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[CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
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[CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
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[CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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@ -4623,6 +4798,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
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&g12b_cpub_clk_trace,
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&sm1_gp1_pll_dco,
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&sm1_gp1_pll,
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&sm1_dsu_clk_premux0,
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&sm1_dsu_clk_premux1,
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&sm1_dsu_clk_mux0_div,
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&sm1_dsu_clk_postmux0,
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&sm1_dsu_clk_mux1_div,
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&sm1_dsu_clk_postmux1,
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&sm1_dsu_clk_dyn,
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&sm1_dsu_final_clk,
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&sm1_dsu_clk,
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};
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static const struct reg_sequence g12a_init_regs[] = {
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@ -80,6 +80,11 @@
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#define HHI_SYS_CPUB_CLK_CNTL1 0x200
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#define HHI_SYS_CPUB_CLK_CNTL 0x208
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#define HHI_VPU_CLKB_CNTL 0x20C
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#define HHI_SYS_CPU_CLK_CNTL2 0x210
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#define HHI_SYS_CPU_CLK_CNTL3 0x214
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#define HHI_SYS_CPU_CLK_CNTL4 0x218
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#define HHI_SYS_CPU_CLK_CNTL5 0x21c
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#define HHI_SYS_CPU_CLK_CNTL6 0x220
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#define HHI_GEN_CLK_CNTL 0x228
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#define HHI_VDIN_MEAS_CLK_CNTL 0x250
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#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
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@ -242,8 +247,16 @@
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#define CLKID_CPUB_CLK_TRACE_SEL 240
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#define CLKID_CPUB_CLK_TRACE 241
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#define CLKID_GP1_PLL_DCO 242
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#define CLKID_DSU_CLK_DYN0_SEL 244
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#define CLKID_DSU_CLK_DYN0_DIV 245
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#define CLKID_DSU_CLK_DYN0 246
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#define CLKID_DSU_CLK_DYN1_SEL 247
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#define CLKID_DSU_CLK_DYN1_DIV 248
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#define CLKID_DSU_CLK_DYN1 249
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#define CLKID_DSU_CLK_DYN 250
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#define CLKID_DSU_CLK_FINAL 251
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#define NR_CLKS 244
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#define NR_CLKS 253
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/g12a-clkc.h>
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