drm/i915/skl: Support Y tiling in MMIO flips
Add Y tiling support to skl_do_mmio_flip. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Cc: Sonika Jindal <sonika.jindal@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -10556,23 +10556,34 @@ static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
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struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
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struct drm_i915_gem_object *obj = intel_fb->obj;
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const enum pipe pipe = intel_crtc->pipe;
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u32 ctl, stride;
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ctl = I915_READ(PLANE_CTL(pipe, 0));
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ctl &= ~PLANE_CTL_TILED_MASK;
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if (obj->tiling_mode == I915_TILING_X)
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switch (fb->modifier[0]) {
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case DRM_FORMAT_MOD_NONE:
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break;
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case I915_FORMAT_MOD_X_TILED:
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ctl |= PLANE_CTL_TILED_X;
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break;
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case I915_FORMAT_MOD_Y_TILED:
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ctl |= PLANE_CTL_TILED_Y;
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break;
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case I915_FORMAT_MOD_Yf_TILED:
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ctl |= PLANE_CTL_TILED_YF;
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break;
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default:
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MISSING_CASE(fb->modifier[0]);
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}
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/*
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* The stride is either expressed as a multiple of 64 bytes chunks for
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* linear buffers or in number of tiles for tiled buffers.
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*/
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stride = fb->pitches[0] >> 6;
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if (obj->tiling_mode == I915_TILING_X)
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stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
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stride = fb->pitches[0] /
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intel_fb_stride_alignment(dev, fb->modifier[0],
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fb->pixel_format);
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/*
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* Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
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