drm/amd/display: change non_dpm0 state's default SR latency
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -37,8 +37,8 @@
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/* Defaults from spreadsheet rev#247 */
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const struct dcn_soc_bounding_box dcn10_soc_defaults = {
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/* latencies */
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.sr_exit_time = 17, /*us*/
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.sr_enter_plus_exit_time = 19, /*us*/
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.sr_exit_time = 13, /*us*/
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.sr_enter_plus_exit_time = 15, /*us*/
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.urgent_latency = 4, /*us*/
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.dram_clock_change_latency = 17, /*us*/
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.write_back_latency = 12, /*us*/
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