mlxsw: reg: Add the Router Multicast Forwarding Table Version 2 register
The RMFT-V2 register is used to configure and query the multicast table and will be used by the multicast router offloading logic. Signed-off-by: Yotam Gigi <yotamg@mellanox.com> Reviewed-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yotam Gigi
David S. Miller
parent
771ced742a
commit
2e654e33c5
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@ -5728,6 +5728,147 @@ static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
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mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
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}
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/* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register
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* --------------------------------------------------------------
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* The RMFT_V2 register is used to configure and query the multicast table.
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*/
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#define MLXSW_REG_RMFT2_ID 0x8027
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#define MLXSW_REG_RMFT2_LEN 0x174
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MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
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/* reg_rmft2_v
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* Valid
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
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enum mlxsw_reg_rmft2_type {
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MLXSW_REG_RMFT2_TYPE_IPV4,
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MLXSW_REG_RMFT2_TYPE_IPV6
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};
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/* reg_rmft2_type
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* Access: Index
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*/
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MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
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enum mlxsw_sp_reg_rmft2_op {
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/* For Write:
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* Write operation. Used to write a new entry to the table. All RW
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* fields are relevant for new entry. Activity bit is set for new
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* entries - Note write with v (Valid) 0 will delete the entry.
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* For Query:
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* Read operation
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*/
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MLXSW_REG_RMFT2_OP_READ_WRITE,
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};
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/* reg_rmft2_op
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* Operation.
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* Access: OP
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*/
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MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
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/* reg_rmft2_a
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* Activity. Set for new entries. Set if a packet lookup has hit on the specific
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* entry.
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* Access: RO
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*/
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MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
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/* reg_rmft2_offset
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* Offset within the multicast forwarding table to write to.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
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/* reg_rmft2_virtual_router
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* Virtual Router ID. Range from 0..cap_max_virtual_routers-1
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
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enum mlxsw_reg_rmft2_irif_mask {
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MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
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MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
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};
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/* reg_rmft2_irif_mask
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* Ingress RIF mask.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
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/* reg_rmft2_irif
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* Ingress RIF index.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
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/* reg_rmft2_dip4
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* Destination IPv4 address
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
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/* reg_rmft2_dip4_mask
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* A bit that is set directs the TCAM to compare the corresponding bit in key. A
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* bit that is clear directs the TCAM to ignore the corresponding bit in key.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
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/* reg_rmft2_sip4
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* Source IPv4 address
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
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/* reg_rmft2_sip4_mask
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* A bit that is set directs the TCAM to compare the corresponding bit in key. A
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* bit that is clear directs the TCAM to ignore the corresponding bit in key.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
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/* reg_rmft2_flexible_action_set
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* ACL action set. The only supported action types in this field and in any
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* action-set pointed from here are as follows:
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* 00h: ACTION_NULL
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* 01h: ACTION_MAC_TTL, only TTL configuration is supported.
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* 03h: ACTION_TRAP
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* 06h: ACTION_QOS
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* 08h: ACTION_POLICING_MONITORING
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* 10h: ACTION_ROUTER_MC
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* Access: RW
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*/
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MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
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MLXSW_REG_FLEX_ACTION_SET_LEN);
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static inline void
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mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
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enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
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u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
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const char *flexible_action_set)
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{
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MLXSW_REG_ZERO(rmft2, payload);
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mlxsw_reg_rmft2_v_set(payload, v);
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mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
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mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
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mlxsw_reg_rmft2_offset_set(payload, offset);
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mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
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mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
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mlxsw_reg_rmft2_irif_set(payload, irif);
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mlxsw_reg_rmft2_dip4_set(payload, dip4);
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mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
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mlxsw_reg_rmft2_sip4_set(payload, sip4);
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mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
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if (flexible_action_set)
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mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
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flexible_action_set);
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}
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/* MFCR - Management Fan Control Register
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* --------------------------------------
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* This register controls the settings of the Fan Speed PWM mechanism.
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@ -7000,6 +7141,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(raleu),
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MLXSW_REG(rauhtd),
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MLXSW_REG(rigr2),
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MLXSW_REG(rmft2),
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MLXSW_REG(mfcr),
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MLXSW_REG(mfsc),
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MLXSW_REG(mfsm),
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