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ASoC: mediatek: mt8188: add required clocks 

apll2_d4, apll12_div4, top_a2sys and top_aud_iec are possibly used in
the future. To prevent from breaking binding ABI after any mt8188 dts
upstream, add these clocks to clock list in advance.

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com
Link: https://lore.kernel.org/r/20230510035526.18137-8-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org
This commit is contained in:
Trevor Wu 2023-05-10 11:55:24 +08:00 committed by Mark Brown
parent fb167449ce
commit 2e5c422a62
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GPG Key ID: 24D68B725D5487D0
2 changed files with 8 additions and 0 deletions
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4
sound/soc/mediatek/mt8188/mt8188-afe-clk.c
View File

@ -25,14 +25,18 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
/* divider */
[MT8188_CLK_TOP_APLL1_D4] = "apll1_d4",
[MT8188_CLK_TOP_APLL2_D4] = "apll2_d4",
[MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0",
[MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1",
[MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2",
[MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3",
[MT8188_CLK_TOP_APLL12_DIV4] = "apll12_div4",
[MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9",
/* mux */
[MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp",
[MT8188_CLK_TOP_A2SYS_SEL] = "top_a2sys",
[MT8188_CLK_TOP_AUD_IEC_SEL] = "top_aud_iec",
[MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus",
[MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h",
[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus",

4
sound/soc/mediatek/mt8188/mt8188-afe-clk.h
View File

@ -23,13 +23,17 @@ enum {
MT8188_CLK_APMIXED_APLL2,
/* divider */
MT8188_CLK_TOP_APLL1_D4,
MT8188_CLK_TOP_APLL2_D4,
MT8188_CLK_TOP_APLL12_DIV0,
MT8188_CLK_TOP_APLL12_DIV1,
MT8188_CLK_TOP_APLL12_DIV2,
MT8188_CLK_TOP_APLL12_DIV3,
MT8188_CLK_TOP_APLL12_DIV4,
MT8188_CLK_TOP_APLL12_DIV9,
/* mux */
MT8188_CLK_TOP_A1SYS_HP_SEL,
MT8188_CLK_TOP_A2SYS_SEL,
MT8188_CLK_TOP_AUD_IEC_SEL,
MT8188_CLK_TOP_AUD_INTBUS_SEL,
MT8188_CLK_TOP_AUDIO_H_SEL,
MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL,