From 2e4b2f7b570a58fc67f25c04a1f6ee93a0938caa Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 24 Mar 2021 16:51:52 +0800 Subject: [PATCH] drm/amd/pm: unify the interface for loading SMU microcode No need to have special handling for swSMU supported ASICs. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++---- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 5 ++- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 4 --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 +++++++++++------------ 4 files changed, 26 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index aae6403f0421..e8c090f90d40 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7170,16 +7170,10 @@ static int gfx_v10_0_hw_init(void *handle) * loaded firstly, so in direct type, it has to load smc ucode * here before rlc. */ - if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) { - r = smu_load_microcode(&adev->smu); + if (!(adev->flags & AMD_IS_APU)) { + r = amdgpu_pm_load_smu_firmware(adev, NULL); if (r) return r; - - r = smu_check_fw_status(&adev->smu); - if (r) { - pr_err("SMC firmware status is not correct\n"); - return r; - } } gfx_v10_0_disable_gpa_mode(adev); } diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 0a6bb3311f0f..464fc04fb334 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -1606,7 +1606,10 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_versio pr_err("smu firmware loading failed\n"); return r; } - *smu_version = adev->pm.fw_version; + + if (smu_version) + *smu_version = adev->pm.fw_version; } + return 0; } diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 65672bb46337..4dc6ce447b2c 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -1252,10 +1252,6 @@ enum smu_cmn2asic_mapping_type { [profile] = {1, (workload)} #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) -int smu_load_microcode(struct smu_context *smu); - -int smu_check_fw_status(struct smu_context *smu); - int smu_get_power_limit(struct smu_context *smu, uint32_t *limit, enum smu_ppt_limit_level limit_level); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 4a3037ea5a90..25237f64a81b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2095,36 +2095,34 @@ const struct amdgpu_ip_block_version smu_v13_0_ip_block = .funcs = &smu_ip_funcs, }; -int smu_load_microcode(struct smu_context *smu) +static int smu_load_microcode(void *handle) { + struct smu_context *smu = handle; + struct amdgpu_device *adev = smu->adev; int ret = 0; - if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) + if (!smu->pm_enabled) return -EOPNOTSUPP; - mutex_lock(&smu->mutex); + /* This should be used for non PSP loading */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) + return 0; - if (smu->ppt_funcs->load_microcode) + if (smu->ppt_funcs->load_microcode) { ret = smu->ppt_funcs->load_microcode(smu); + if (ret) { + dev_err(adev->dev, "Load microcode failed\n"); + return ret; + } + } - mutex_unlock(&smu->mutex); - - return ret; -} - -int smu_check_fw_status(struct smu_context *smu) -{ - int ret = 0; - - if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) - return -EOPNOTSUPP; - - mutex_lock(&smu->mutex); - - if (smu->ppt_funcs->check_fw_status) + if (smu->ppt_funcs->check_fw_status) { ret = smu->ppt_funcs->check_fw_status(smu); - - mutex_unlock(&smu->mutex); + if (ret) { + dev_err(adev->dev, "SMC is not ready\n"); + return ret; + } + } return ret; } @@ -2981,6 +2979,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = { .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, + .load_firmware = smu_load_microcode, }; int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,