platform/x86: intel_pmc_core: Dump low power status registers on an S0ix.y failure
Platforms prior to Tiger Lake has no sub-states of S0ix and accessing device PM states that are latched whenever there is a PC10 entry is possible with the help of slp_s0_debug_status and slp_s0_dbg_latch debugfs entries. If a platform has sub-states of S0ix, no such entries are created. Hence, dump low power status registers on resume When any attempt to enter any low power state was unsuccessful. Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: David Box <david.e.box@intel.com> Suggested-by: David Box <david.e.box@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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@ -1285,6 +1285,8 @@ static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
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static int pmc_core_resume(struct device *dev)
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{
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struct pmc_dev *pmcdev = dev_get_drvdata(dev);
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const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
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int offset = pmcdev->map->lpm_status_offset;
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if (!pmcdev->check_counters)
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return 0;
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@ -1304,6 +1306,8 @@ static int pmc_core_resume(struct device *dev)
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pmcdev->s0ix_counter);
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if (pmcdev->map->slps0_dbg_maps)
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pmc_core_slps0_display(pmcdev, dev, NULL);
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if (pmcdev->map->lpm_sts)
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pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps);
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return 0;
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}
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