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net: dp83869: Fix RGMII internal delay configuration 

The RGMII control register at 0x32 indicates the states for the bits
RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY as follows:

  RGMII Transmit/Receive Clock Delay
    0x0 = RGMII transmit clock is shifted with respect to transmit/receive data.
    0x1 = RGMII transmit clock is aligned with respect to transmit/receive data.

This commit fixes the inversed behavior of these bits

Fixes: 736b25afe2 ("net: dp83869: Add RGMII internal delay configuration")
Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
Acked-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Daniel Gorsulowski 2020-08-26 07:00:14 +02:00 committed by David S. Miller
parent 9f13457377
commit 2e1ec861a6
1 changed files with 6 additions and 6 deletions
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12
drivers/net/phy/dp83869.c
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@ -427,18 +427,18 @@ static int dp83869_config_init(struct phy_device *phydev)
return ret;
val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
DP83869_RGMII_RX_CLK_DELAY_EN);
val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
DP83869_RGMII_RX_CLK_DELAY_EN);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
DP83869_RGMII_RX_CLK_DELAY_EN);
val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
DP83869_RGMII_RX_CLK_DELAY_EN);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
val |= DP83869_RGMII_TX_CLK_DELAY_EN;
val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
val |= DP83869_RGMII_RX_CLK_DELAY_EN;
val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
val);