drm/i915/tgl: Wa_1409600907
To avoid possible hang, we need to add depth stall if we flush the depth cache. Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-8-mika.kuoppala@linux.intel.com
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@ -3203,6 +3203,8 @@ static int gen12_emit_flush_render(struct i915_request *request,
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flags |= PIPE_CONTROL_TILE_CACHE_FLUSH;
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flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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/* Wa_1409600907:tgl */
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flags |= PIPE_CONTROL_DEPTH_STALL;
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flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_FLUSH_ENABLE;
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flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
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@ -3435,6 +3437,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
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PIPE_CONTROL_TILE_CACHE_FLUSH |
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PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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/* Wa_1409600907:tgl */
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PIPE_CONTROL_DEPTH_STALL |
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PIPE_CONTROL_DC_FLUSH_ENABLE |
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PIPE_CONTROL_FLUSH_ENABLE |
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PIPE_CONTROL_HDC_PIPELINE_FLUSH);
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