Merge branch 'drm-fixes-5.1' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Fixes for 5.1: - Fix for pcie dpm - Powerplay fixes for vega20 - Fix vbios display on reboot if driver display state is retained - Gfx9 resume robustness fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190404042939.3386-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
2ded18812b
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@ -3625,6 +3625,7 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
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struct pci_dev *pdev = adev->pdev;
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enum pci_bus_speed cur_speed;
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enum pcie_link_width cur_width;
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u32 ret = 1;
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*speed = PCI_SPEED_UNKNOWN;
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*width = PCIE_LNK_WIDTH_UNKNOWN;
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@ -3632,6 +3633,10 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev,
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while (pdev) {
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cur_speed = pcie_get_speed_cap(pdev);
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cur_width = pcie_get_width_cap(pdev);
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ret = pcie_bandwidth_available(adev->pdev, NULL,
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NULL, &cur_width);
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if (!ret)
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cur_width = PCIE_LNK_WIDTH_RESRV;
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if (cur_speed != PCI_SPEED_UNKNOWN) {
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if (*speed == PCI_SPEED_UNKNOWN)
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@ -2405,8 +2405,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
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/* disable CG */
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WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
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adev->gfx.rlc.funcs->reset(adev);
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gfx_v9_0_init_pg(adev);
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
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@ -2660,12 +2660,18 @@ void core_link_enable_stream(
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void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
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{
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struct dc *core_dc = pipe_ctx->stream->ctx->dc;
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struct dc_stream_state *stream = pipe_ctx->stream;
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core_dc->hwss.blank_stream(pipe_ctx);
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if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
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deallocate_mst_payload(pipe_ctx);
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if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
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dal_ddc_service_write_scdc_data(
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stream->link->ddc, 0,
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stream->timing.flags.LTE_340MCSC_SCRAMBLE);
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core_dc->hwss.disable_stream(pipe_ctx, option);
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disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
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@ -91,6 +91,12 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
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* MP0CLK DS
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*/
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data->registry_data.disallowed_features = 0xE0041C00;
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/* ECC feature should be disabled on old SMUs */
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
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hwmgr->smu_version = smum_get_argument(hwmgr);
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if (hwmgr->smu_version < 0x282100)
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data->registry_data.disallowed_features |= FEATURE_ECC_MASK;
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data->registry_data.od_state_in_dc_support = 0;
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data->registry_data.thermal_support = 1;
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data->registry_data.skip_baco_hardware = 0;
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@ -357,6 +363,7 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
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data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;
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data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;
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data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;
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data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;
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for (i = 0; i < GNLD_FEATURES_MAX; i++) {
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data->smu_features[i].smu_feature_bitmap =
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@ -3020,7 +3027,8 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
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"FCLK_DS",
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"MP1CLK_DS",
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"MP0CLK_DS",
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"XGMI"};
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"XGMI",
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"ECC"};
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static const char *output_title[] = {
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"FEATURES",
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"BITMASK",
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@ -3462,6 +3470,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
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struct vega20_single_dpm_table *dpm_table;
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bool vblank_too_short = false;
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bool disable_mclk_switching;
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bool disable_fclk_switching;
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uint32_t i, latency;
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disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
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@ -3537,13 +3546,20 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
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if (hwmgr->display_config->nb_pstate_switch_disable)
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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if ((disable_mclk_switching &&
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(dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||
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hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
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disable_fclk_switching = true;
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else
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disable_fclk_switching = false;
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/* fclk */
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dpm_table = &(data->dpm_table.fclk_table);
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;
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dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
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dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;
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if (hwmgr->display_config->nb_pstate_switch_disable)
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if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
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dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
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/* vclk */
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@ -80,6 +80,7 @@ enum {
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GNLD_DS_MP1CLK,
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GNLD_DS_MP0CLK,
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GNLD_XGMI,
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GNLD_ECC,
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GNLD_FEATURES_MAX
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};
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@ -99,7 +99,7 @@
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#define FEATURE_DS_MP1CLK_BIT 30
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#define FEATURE_DS_MP0CLK_BIT 31
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#define FEATURE_XGMI_BIT 32
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#define FEATURE_SPARE_33_BIT 33
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#define FEATURE_ECC_BIT 33
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#define FEATURE_SPARE_34_BIT 34
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#define FEATURE_SPARE_35_BIT 35
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#define FEATURE_SPARE_36_BIT 36
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@ -165,7 +165,8 @@
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#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
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#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
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#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
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#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT )
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#define FEATURE_XGMI_MASK (1ULL << FEATURE_XGMI_BIT )
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#define FEATURE_ECC_MASK (1ULL << FEATURE_ECC_BIT )
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#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
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#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
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