LoongArch: KVM: Add EXTIOI read and write functions
Upstream: no Implementation of EXTIOI interrupt controller address space read and write function simulation. Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
This commit is contained in:
Xianglai Li
parent
59537b43c2
commit
2dc138292b
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@ -19,8 +19,25 @@
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#define EXTIOI_BASE 0x1400
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#define EXTIOI_SIZE 0x900
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#define EXTIOI_NODETYPE_START 0xa0
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#define EXTIOI_NODETYPE_END 0xbf
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#define EXTIOI_IPMAP_START 0xc0
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#define EXTIOI_IPMAP_END 0xc7
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#define EXTIOI_ENABLE_START 0x200
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#define EXTIOI_ENABLE_END 0x21f
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#define EXTIOI_BOUNCE_START 0x280
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#define EXTIOI_BOUNCE_END 0x29f
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#define EXTIOI_ISR_START 0x300
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#define EXTIOI_ISR_END 0x31f
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#define EXTIOI_COREISR_START 0x400
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#define EXTIOI_COREISR_END 0x71f
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#define EXTIOI_COREMAP_START 0x800
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#define EXTIOI_COREMAP_END 0x8ff
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#define LS3A_INTC_IP 8
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#define EXTIOI_SW_COREMAP_FLAG (1 << 0)
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struct loongarch_extioi {
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spinlock_t lock;
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struct kvm *kvm;
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@ -42,6 +42,8 @@ struct kvm_vm_stat {
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u64 hugepages;
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u64 ipi_read_exits;
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u64 ipi_write_exits;
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u64 extioi_read_exits;
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u64 extioi_write_exits;
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};
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struct kvm_vcpu_stat {
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@ -7,18 +7,591 @@
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#include <asm/kvm_vcpu.h>
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#include <linux/count_zeros.h>
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#define loongarch_ext_irq_lock(s, flags) spin_lock_irqsave(&s->lock, flags)
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#define loongarch_ext_irq_unlock(s, flags) spin_unlock_irqrestore(&s->lock, flags)
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static void extioi_update_irq(struct loongarch_extioi *s, int irq, int level)
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{
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int ipnum, cpu, found, irq_index, irq_mask;
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struct kvm_interrupt vcpu_irq;
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struct kvm_vcpu *vcpu;
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ipnum = s->ipmap.reg_u8[irq / 32];
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ipnum = count_trailing_zeros(ipnum);
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ipnum = (ipnum >= 0 && ipnum < 4) ? ipnum : 0;
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cpu = s->sw_coremap[irq];
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vcpu = kvm_get_vcpu(s->kvm, cpu);
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irq_index = irq / 32;
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/* length of accessing core isr is 4 bytes */
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irq_mask = 1 << (irq & 0x1f);
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if (level) {
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/* if not enable return false */
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if (((s->enable.reg_u32[irq_index]) & irq_mask) == 0)
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return;
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s->coreisr.reg_u32[cpu][irq_index] |= irq_mask;
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found = find_first_bit(s->sw_coreisr[cpu][ipnum], EXTIOI_IRQS);
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set_bit(irq, s->sw_coreisr[cpu][ipnum]);
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} else {
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s->coreisr.reg_u32[cpu][irq_index] &= ~irq_mask;
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clear_bit(irq, s->sw_coreisr[cpu][ipnum]);
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found = find_first_bit(s->sw_coreisr[cpu][ipnum], EXTIOI_IRQS);
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}
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if (found < EXTIOI_IRQS)
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/* other irq is handling, need not update parent irq level */
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return;
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vcpu_irq.irq = level ? INT_HWI0 + ipnum : -(INT_HWI0 + ipnum);
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kvm_vcpu_ioctl_interrupt(vcpu, &vcpu_irq);
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}
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void extioi_set_irq(struct loongarch_extioi *s, int irq, int level)
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{
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unsigned long *isr = (unsigned long *)s->isr.reg_u8;
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unsigned long flags;
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level ? set_bit(irq, isr) : clear_bit(irq, isr);
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if (!level)
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return;
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loongarch_ext_irq_lock(s, flags);
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extioi_update_irq(s, irq, level);
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loongarch_ext_irq_unlock(s, flags);
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}
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static inline void extioi_enable_irq(struct kvm_vcpu *vcpu, struct loongarch_extioi *s,
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int index, u8 mask, int level)
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{
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u8 val;
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int irq;
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val = mask & s->isr.reg_u8[index];
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irq = ffs(val);
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while (irq != 0) {
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/*
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* enable bit change from 0 to 1,
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* need to update irq by pending bits
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*/
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extioi_update_irq(s, irq - 1 + index * 8, level);
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val &= ~(1 << (irq - 1));
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irq = ffs(val);
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}
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}
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static int loongarch_extioi_writeb(struct kvm_vcpu *vcpu,
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struct loongarch_extioi *s,
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gpa_t addr, int len, const void *val)
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{
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int index, irq, ret = 0;
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u8 data, old_data, cpu;
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u8 coreisr, old_coreisr;
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gpa_t offset;
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data = *(u8 *)val;
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offset = addr - EXTIOI_BASE;
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switch (offset) {
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case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END:
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index = (offset - EXTIOI_NODETYPE_START);
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s->nodetype.reg_u8[index] = data;
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break;
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case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END:
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/*
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* ipmap cannot be set at runtime, can be set only at the beginning
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* of intr driver, need not update upper irq level
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*/
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index = (offset - EXTIOI_IPMAP_START);
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s->ipmap.reg_u8[index] = data;
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break;
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case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END:
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index = (offset - EXTIOI_ENABLE_START);
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old_data = s->enable.reg_u8[index];
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s->enable.reg_u8[index] = data;
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/*
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* 1: enable irq.
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* update irq when isr is set.
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*/
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data = s->enable.reg_u8[index] & ~old_data & s->isr.reg_u8[index];
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extioi_enable_irq(vcpu, s, index, data, 1);
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/*
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* 0: disable irq.
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* update irq when isr is set.
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*/
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data = ~s->enable.reg_u8[index] & old_data & s->isr.reg_u8[index];
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extioi_enable_irq(vcpu, s, index, data, 0);
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break;
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case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END:
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/* do not emulate hw bounced irq routing */
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index = offset - EXTIOI_BOUNCE_START;
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s->bounce.reg_u8[index] = data;
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break;
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case EXTIOI_COREISR_START ... EXTIOI_COREISR_END:
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/* length of accessing core isr is 8 bytes */
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index = (offset - EXTIOI_COREISR_START);
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/* using attrs to get current cpu index */
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cpu = vcpu->vcpu_id;
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coreisr = data;
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old_coreisr = s->coreisr.reg_u8[cpu][index];
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/* write 1 to clear interrupt */
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s->coreisr.reg_u8[cpu][index] = old_coreisr & ~coreisr;
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coreisr &= old_coreisr;
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irq = ffs(coreisr);
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while (irq != 0) {
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extioi_update_irq(s, irq - 1 + index * 8, 0);
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coreisr &= ~(1 << (irq - 1));
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irq = ffs(coreisr);
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}
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break;
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case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END:
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irq = offset - EXTIOI_COREMAP_START;
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index = irq;
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s->coremap.reg_u8[index] = data;
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cpu = data & 0xff;
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cpu = ffs(cpu) - 1;
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cpu = (cpu >= 4) ? 0 : cpu;
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if (s->sw_coremap[irq] == cpu)
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break;
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if (test_bit(irq, (unsigned long *)s->isr.reg_u8)) {
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/*
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* lower irq at old cpu and raise irq at new cpu
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*/
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extioi_update_irq(s, irq, 0);
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s->sw_coremap[irq] = cpu;
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extioi_update_irq(s, irq, 1);
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} else
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s->sw_coremap[irq] = cpu;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int loongarch_extioi_writew(struct kvm_vcpu *vcpu,
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struct loongarch_extioi *s,
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gpa_t addr, int len, const void *val)
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{
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int i, index, irq, ret = 0;
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u8 cpu;
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u32 data, old_data;
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u32 coreisr, old_coreisr;
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gpa_t offset;
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data = *(u32 *)val;
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offset = addr - EXTIOI_BASE;
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switch (offset) {
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case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END:
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index = (offset - EXTIOI_NODETYPE_START) >> 2;
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s->nodetype.reg_u32[index] = data;
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break;
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case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END:
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/*
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* ipmap cannot be set at runtime, can be set only at the beginning
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* of intr driver, need not update upper irq level
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*/
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index = (offset - EXTIOI_IPMAP_START) >> 2;
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s->ipmap.reg_u32[index] = data;
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break;
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case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END:
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index = (offset - EXTIOI_ENABLE_START) >> 2;
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old_data = s->enable.reg_u32[index];
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s->enable.reg_u32[index] = data;
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/*
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* 1: enable irq.
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* update irq when isr is set.
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*/
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data = s->enable.reg_u32[index] & ~old_data & s->isr.reg_u32[index];
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index = index << 2;
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for (i = 0; i < sizeof(data); i++) {
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u8 mask = (data >> (i * 8)) & 0xff;
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extioi_enable_irq(vcpu, s, index + i, mask, 1);
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}
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/*
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* 0: disable irq.
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* update irq when isr is set.
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*/
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data = ~s->enable.reg_u32[index] & old_data & s->isr.reg_u32[index];
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for (i = 0; i < sizeof(data); i++) {
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u8 mask = (data >> (i * 8)) & 0xff;
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extioi_enable_irq(vcpu, s, index, mask, 0);
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}
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break;
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case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END:
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/* do not emulate hw bounced irq routing */
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index = (offset - EXTIOI_BOUNCE_START) >> 2;
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s->bounce.reg_u32[index] = data;
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break;
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case EXTIOI_COREISR_START ... EXTIOI_COREISR_END:
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/* length of accessing core isr is 8 bytes */
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index = (offset - EXTIOI_COREISR_START) >> 2;
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/* using attrs to get current cpu index */
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cpu = vcpu->vcpu_id;
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coreisr = data;
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old_coreisr = s->coreisr.reg_u32[cpu][index];
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/* write 1 to clear interrupt */
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s->coreisr.reg_u32[cpu][index] = old_coreisr & ~coreisr;
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coreisr &= old_coreisr;
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irq = ffs(coreisr);
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while (irq != 0) {
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extioi_update_irq(s, irq - 1 + index * 32, 0);
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coreisr &= ~(1 << (irq - 1));
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irq = ffs(coreisr);
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}
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break;
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case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END:
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irq = offset - EXTIOI_COREMAP_START;
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index = irq >> 2;
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s->coremap.reg_u32[index] = data;
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for (i = 0; i < sizeof(data); i++) {
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cpu = data & 0xff;
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cpu = ffs(cpu) - 1;
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cpu = (cpu >= 4) ? 0 : cpu;
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data = data >> 8;
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if (s->sw_coremap[irq + i] == cpu)
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continue;
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if (test_bit(irq, (unsigned long *)s->isr.reg_u8)) {
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/*
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* lower irq at old cpu and raise irq at new cpu
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*/
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extioi_update_irq(s, irq + i, 0);
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s->sw_coremap[irq + i] = cpu;
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extioi_update_irq(s, irq + i, 1);
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} else
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s->sw_coremap[irq + i] = cpu;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int loongarch_extioi_writel(struct kvm_vcpu *vcpu,
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struct loongarch_extioi *s,
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gpa_t addr, int len, const void *val)
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{
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int i, index, irq, bits, ret = 0;
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u8 cpu;
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u64 data, old_data;
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u64 coreisr, old_coreisr;
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gpa_t offset;
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data = *(u64 *)val;
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offset = addr - EXTIOI_BASE;
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switch (offset) {
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case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END:
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index = (offset - EXTIOI_NODETYPE_START) >> 3;
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s->nodetype.reg_u64[index] = data;
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break;
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case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END:
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/*
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* ipmap cannot be set at runtime, can be set only at the beginning
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* of intr driver, need not update upper irq level
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*/
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index = (offset - EXTIOI_IPMAP_START) >> 3;
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s->ipmap.reg_u64 = data;
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break;
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case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END:
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index = (offset - EXTIOI_ENABLE_START) >> 3;
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old_data = s->enable.reg_u64[index];
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s->enable.reg_u64[index] = data;
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/*
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* 1: enable irq.
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* update irq when isr is set.
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*/
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data = s->enable.reg_u64[index] & ~old_data & s->isr.reg_u64[index];
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index = index << 3;
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for (i = 0; i < sizeof(data); i++) {
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u8 mask = (data >> (i * 8)) & 0xff;
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extioi_enable_irq(vcpu, s, index + i, mask, 1);
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}
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/*
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* 0: disable irq.
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* update irq when isr is set.
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*/
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data = ~s->enable.reg_u64[index] & old_data & s->isr.reg_u64[index];
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for (i = 0; i < sizeof(data); i++) {
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u8 mask = (data >> (i * 8)) & 0xff;
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extioi_enable_irq(vcpu, s, index, mask, 0);
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}
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break;
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case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END:
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/* do not emulate hw bounced irq routing */
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index = (offset - EXTIOI_BOUNCE_START) >> 3;
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s->bounce.reg_u64[index] = data;
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break;
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case EXTIOI_COREISR_START ... EXTIOI_COREISR_END:
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/* length of accessing core isr is 8 bytes */
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index = (offset - EXTIOI_COREISR_START) >> 3;
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/* using attrs to get current cpu index */
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cpu = vcpu->vcpu_id;
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coreisr = data;
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old_coreisr = s->coreisr.reg_u64[cpu][index];
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/* write 1 to clear interrupt */
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s->coreisr.reg_u64[cpu][index] = old_coreisr & ~coreisr;
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coreisr &= old_coreisr;
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bits = sizeof(u64) * 8;
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irq = find_first_bit((void *)&coreisr, bits);
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while (irq < bits) {
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extioi_update_irq(s, irq + index * bits, 0);
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bitmap_clear((void *)&coreisr, irq, 1);
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irq = find_first_bit((void *)&coreisr, bits);
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}
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break;
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case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END:
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irq = offset - EXTIOI_COREMAP_START;
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index = irq >> 3;
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s->coremap.reg_u64[index] = data;
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for (i = 0; i < sizeof(data); i++) {
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cpu = data & 0xff;
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cpu = ffs(cpu) - 1;
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cpu = (cpu >= 4) ? 0 : cpu;
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data = data >> 8;
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if (s->sw_coremap[irq + i] == cpu)
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continue;
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if (test_bit(irq, (unsigned long *)s->isr.reg_u8)) {
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/*
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* lower irq at old cpu and raise irq at new cpu
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*/
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extioi_update_irq(s, irq + i, 0);
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s->sw_coremap[irq + i] = cpu;
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extioi_update_irq(s, irq + i, 1);
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} else
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s->sw_coremap[irq + i] = cpu;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int kvm_loongarch_extioi_write(struct kvm_vcpu *vcpu,
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struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, const void *val)
|
||||
{
|
||||
return 0;
|
||||
int ret;
|
||||
struct loongarch_extioi *extioi = vcpu->kvm->arch.extioi;
|
||||
unsigned long flags;
|
||||
|
||||
if (!extioi) {
|
||||
kvm_err("%s: extioi irqchip not valid!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
vcpu->kvm->stat.extioi_write_exits++;
|
||||
loongarch_ext_irq_lock(extioi, flags);
|
||||
|
||||
switch (len) {
|
||||
case 1:
|
||||
ret = loongarch_extioi_writeb(vcpu, extioi, addr, len, val);
|
||||
break;
|
||||
case 4:
|
||||
ret = loongarch_extioi_writew(vcpu, extioi, addr, len, val);
|
||||
break;
|
||||
case 8:
|
||||
ret = loongarch_extioi_writel(vcpu, extioi, addr, len, val);
|
||||
break;
|
||||
default:
|
||||
WARN_ONCE(1, "%s: Abnormal address access:addr 0x%llx,size %d\n",
|
||||
__func__, addr, len);
|
||||
}
|
||||
|
||||
loongarch_ext_irq_unlock(extioi, flags);
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int loongarch_extioi_readb(struct kvm_vcpu *vcpu, struct loongarch_extioi *s,
|
||||
gpa_t addr, int len, void *val)
|
||||
{
|
||||
int index, ret = 0;
|
||||
gpa_t offset;
|
||||
u64 data;
|
||||
|
||||
offset = addr - EXTIOI_BASE;
|
||||
switch (offset) {
|
||||
case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END:
|
||||
index = offset - EXTIOI_NODETYPE_START;
|
||||
data = s->nodetype.reg_u8[index];
|
||||
break;
|
||||
case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END:
|
||||
index = offset - EXTIOI_IPMAP_START;
|
||||
data = s->ipmap.reg_u8[index];
|
||||
break;
|
||||
case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END:
|
||||
index = offset - EXTIOI_ENABLE_START;
|
||||
data = s->enable.reg_u8[index];
|
||||
break;
|
||||
case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END:
|
||||
index = offset - EXTIOI_BOUNCE_START;
|
||||
data = s->bounce.reg_u8[index];
|
||||
break;
|
||||
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END:
|
||||
/* length of accessing core isr is 8 bytes */
|
||||
index = offset - EXTIOI_COREISR_START;
|
||||
data = s->coreisr.reg_u8[vcpu->vcpu_id][index];
|
||||
break;
|
||||
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END:
|
||||
index = offset - EXTIOI_COREMAP_START;
|
||||
data = s->coremap.reg_u8[index];
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
*(u8 *)val = data;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int loongarch_extioi_readw(struct kvm_vcpu *vcpu, struct loongarch_extioi *s,
|
||||
gpa_t addr, int len, void *val)
|
||||
{
|
||||
int index, ret = 0;
|
||||
gpa_t offset;
|
||||
u64 data;
|
||||
|
||||
offset = addr - EXTIOI_BASE;
|
||||
switch (offset) {
|
||||
case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END:
|
||||
index = (offset - EXTIOI_NODETYPE_START) >> 2;
|
||||
data = s->nodetype.reg_u32[index];
|
||||
break;
|
||||
case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END:
|
||||
index = (offset - EXTIOI_IPMAP_START) >> 2;
|
||||
data = s->ipmap.reg_u32[index];
|
||||
break;
|
||||
case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END:
|
||||
index = (offset - EXTIOI_ENABLE_START) >> 2;
|
||||
data = s->enable.reg_u32[index];
|
||||
break;
|
||||
case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END:
|
||||
index = (offset - EXTIOI_BOUNCE_START) >> 2;
|
||||
data = s->bounce.reg_u32[index];
|
||||
break;
|
||||
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END:
|
||||
/* length of accessing core isr is 8 bytes */
|
||||
index = (offset - EXTIOI_COREISR_START) >> 2;
|
||||
data = s->coreisr.reg_u32[vcpu->vcpu_id][index];
|
||||
break;
|
||||
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END:
|
||||
index = (offset - EXTIOI_COREMAP_START) >> 2;
|
||||
data = s->coremap.reg_u32[index];
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
*(u32 *)val = data;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int loongarch_extioi_readl(struct kvm_vcpu *vcpu, struct loongarch_extioi *s,
|
||||
gpa_t addr, int len, void *val)
|
||||
{
|
||||
int index, ret = 0;
|
||||
gpa_t offset;
|
||||
u64 data;
|
||||
|
||||
offset = addr - EXTIOI_BASE;
|
||||
switch (offset) {
|
||||
case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END:
|
||||
index = (offset - EXTIOI_NODETYPE_START) >> 3;
|
||||
data = s->nodetype.reg_u64[index];
|
||||
break;
|
||||
case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END:
|
||||
index = (offset - EXTIOI_IPMAP_START) >> 3;
|
||||
data = s->ipmap.reg_u64;
|
||||
break;
|
||||
case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END:
|
||||
index = (offset - EXTIOI_ENABLE_START) >> 3;
|
||||
data = s->enable.reg_u64[index];
|
||||
break;
|
||||
case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END:
|
||||
index = (offset - EXTIOI_BOUNCE_START) >> 3;
|
||||
data = s->bounce.reg_u64[index];
|
||||
break;
|
||||
case EXTIOI_COREISR_START ... EXTIOI_COREISR_END:
|
||||
/* length of accessing core isr is 8 bytes */
|
||||
index = (offset - EXTIOI_COREISR_START) >> 3;
|
||||
data = s->coreisr.reg_u64[vcpu->vcpu_id][index];
|
||||
break;
|
||||
case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END:
|
||||
index = (offset - EXTIOI_COREMAP_START) >> 3;
|
||||
data = s->coremap.reg_u64[index];
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
*(u64 *)val = data;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int kvm_loongarch_extioi_read(struct kvm_vcpu *vcpu,
|
||||
struct kvm_io_device *dev,
|
||||
gpa_t addr, int len, void *val)
|
||||
{
|
||||
return 0;
|
||||
int ret;
|
||||
struct loongarch_extioi *extioi = vcpu->kvm->arch.extioi;
|
||||
unsigned long flags;
|
||||
|
||||
if (!extioi) {
|
||||
kvm_err("%s: extioi irqchip not valid!\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
vcpu->kvm->stat.extioi_read_exits++;
|
||||
loongarch_ext_irq_lock(extioi, flags);
|
||||
|
||||
switch (len) {
|
||||
case 1:
|
||||
ret = loongarch_extioi_readb(vcpu, extioi, addr, len, val);
|
||||
break;
|
||||
case 4:
|
||||
ret = loongarch_extioi_readw(vcpu, extioi, addr, len, val);
|
||||
break;
|
||||
case 8:
|
||||
ret = loongarch_extioi_readl(vcpu, extioi, addr, len, val);
|
||||
break;
|
||||
default:
|
||||
WARN_ONCE(1, "%s: Abnormal address access:addr 0x%llx,size %d\n",
|
||||
__func__, addr, len);
|
||||
}
|
||||
|
||||
loongarch_ext_irq_unlock(extioi, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct kvm_io_device_ops kvm_loongarch_extioi_ops = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue