MIPS: Support extended ASIDs
Add support for extended ASIDs as determined by the Config4.AE bit. Since the only supported CPUs known to implement this are Netlogic XLP and MIPS I6400, select this variable ASID support based upon CONFIG_CPU_XLP and CONFIG_CPU_MIPSR6. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Jayachandran C. <jchandra@broadcom.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13211/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
4edf00a46b
commit
2db003a5dd
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@ -1706,6 +1706,7 @@ config CPU_XLP
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select CPU_HAS_PREFETCH
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select CPU_MIPSR2
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select CPU_SUPPORTS_HUGEPAGES
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select MIPS_ASID_BITS_VARIABLE
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help
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Netlogic Microsystems XLP processors.
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endchoice
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@ -2001,6 +2002,7 @@ config CPU_MIPSR6
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bool
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default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
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select HAVE_ARCH_BITREVERSE
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select MIPS_ASID_BITS_VARIABLE
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select MIPS_SPRAM
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config EVA
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@ -2457,9 +2459,13 @@ config MIPS_ASID_SHIFT
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config MIPS_ASID_BITS
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int
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default 0 if MIPS_ASID_BITS_VARIABLE
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default 6 if CPU_R3000 || CPU_TX39XX
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default 8
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config MIPS_ASID_BITS_VARIABLE
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bool
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#
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# - Highmem only makes sense for the 32-bit kernel.
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# - The current highmem code will only work properly on physically indexed
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@ -40,6 +40,9 @@ struct cache_desc {
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struct cpuinfo_mips {
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unsigned long asid_cache;
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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unsigned long asid_mask;
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#endif
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/*
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* Capability and feature descriptor structure for MIPS CPU
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@ -139,7 +142,18 @@ static inline unsigned long cpu_asid_inc(void)
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static inline unsigned long cpu_asid_mask(struct cpuinfo_mips *cpuinfo)
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{
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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return cpuinfo->asid_mask;
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#endif
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return ((1 << CONFIG_MIPS_ASID_BITS) - 1) << CONFIG_MIPS_ASID_SHIFT;
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}
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static inline void set_cpu_asid_mask(struct cpuinfo_mips *cpuinfo,
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unsigned long asid_mask)
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{
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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cpuinfo->asid_mask = asid_mask;
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#endif
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}
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#endif /* __ASM_CPU_INFO_H */
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@ -14,6 +14,7 @@
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#include <linux/mm.h>
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#include <linux/kbuild.h>
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#include <linux/suspend.h>
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#include <asm/cpu-info.h>
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#include <asm/pm.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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@ -338,6 +339,15 @@ void output_pm_defines(void)
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}
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#endif
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void output_cpuinfo_defines(void)
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{
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COMMENT(" MIPS cpuinfo offsets. ");
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DEFINE(CPUINFO_SIZE, sizeof(struct cpuinfo_mips));
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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OFFSET(CPUINFO_ASID_MASK, cpuinfo_mips, asid_mask);
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#endif
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}
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void output_kvm_defines(void)
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{
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COMMENT(" KVM/MIPS Specfic offsets. ");
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@ -732,6 +732,7 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
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unsigned int newcf4;
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unsigned int mmuextdef;
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unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
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unsigned long asid_mask;
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config4 = read_c0_config4();
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@ -792,6 +793,18 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
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c->kscratch_mask = (config4 >> 16) & 0xff;
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asid_mask = MIPS_ENTRYHI_ASID;
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if (config4 & MIPS_CONF4_AE)
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asid_mask |= MIPS_ENTRYHI_ASIDX;
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set_cpu_asid_mask(c, asid_mask);
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/*
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* Warn if the computed ASID mask doesn't match the mask the kernel
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* is built for. This may indicate either a serious problem or an
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* easy optimisation opportunity, but either way should be addressed.
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*/
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WARN_ON(asid_mask != cpu_asid_mask(c));
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return config4 & MIPS_CONF_M;
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}
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@ -455,7 +455,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
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.set noreorder
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/* check if TLB contains a entry for EPC */
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MFC0 k1, CP0_ENTRYHI
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andi k1, MIPS_ENTRYHI_ASID
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andi k1, MIPS_ENTRYHI_ASID | MIPS_ENTRYHI_ASIDX
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MFC0 k0, CP0_EPC
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PTR_SRL k0, _PAGE_SHIFT + 1
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PTR_SLL k0, _PAGE_SHIFT + 1
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@ -137,7 +137,14 @@ FEXPORT(__kvm_mips_load_asid)
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INT_SLL t2, t2, 2 /* x4 */
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REG_ADDU t3, t1, t2
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LONG_L k0, (t3)
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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li t3, CPUINFO_SIZE/4
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mul t2, t2, t3 /* x sizeof(struct cpuinfo_mips)/4 */
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LONG_L t2, (cpu_data + CPUINFO_ASID_MASK)(t2)
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and k0, k0, t2
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#else
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andi k0, k0, MIPS_ENTRYHI_ASID
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#endif
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mtc0 k0, CP0_ENTRYHI
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ehb
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@ -449,7 +456,14 @@ __kvm_mips_return_to_guest:
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INT_SLL t2, t2, 2 /* x4 */
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REG_ADDU t3, t1, t2
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LONG_L k0, (t3)
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#ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
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li t3, CPUINFO_SIZE/4
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mul t2, t2, t3 /* x sizeof(struct cpuinfo_mips)/4 */
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LONG_L t2, (cpu_data + CPUINFO_ASID_MASK)(t2)
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and k0, k0, t2
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#else
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andi k0, k0, MIPS_ENTRYHI_ASID
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#endif
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mtc0 k0, CP0_ENTRYHI
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ehb
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