drm/msm: update generated headers
Resync generated headers to pull in a6xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
2c087a3366
commit
2d75632253
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@ -8,17 +8,19 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2017 by the following authors:
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Copyright (C) 2013-2018 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@ -84,13 +86,12 @@ enum a2xx_sq_surfaceformat {
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FMT_5_5_5_1 = 13,
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FMT_8_8_8_8_A = 14,
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FMT_4_4_4_4 = 15,
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FMT_10_11_11 = 16,
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FMT_11_11_10 = 17,
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FMT_8_8_8 = 16,
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FMT_DXT1 = 18,
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FMT_DXT2_3 = 19,
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FMT_DXT4_5 = 20,
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FMT_10_10_10_2 = 21,
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FMT_24_8 = 22,
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FMT_24_8_FLOAT = 23,
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FMT_16 = 24,
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FMT_16_16 = 25,
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FMT_16_16_16_16 = 26,
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@ -106,29 +107,23 @@ enum a2xx_sq_surfaceformat {
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FMT_32_FLOAT = 36,
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FMT_32_32_FLOAT = 37,
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FMT_32_32_32_32_FLOAT = 38,
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FMT_32_AS_8 = 39,
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FMT_32_AS_8_8 = 40,
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FMT_16_MPEG = 41,
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FMT_16_16_MPEG = 42,
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FMT_8_INTERLACED = 43,
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FMT_32_AS_8_INTERLACED = 44,
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FMT_32_AS_8_8_INTERLACED = 45,
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FMT_16_INTERLACED = 46,
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FMT_16_MPEG_INTERLACED = 47,
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FMT_16_16_MPEG_INTERLACED = 48,
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FMT_ATI_TC_RGB = 39,
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FMT_ATI_TC_RGBA = 40,
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FMT_ATI_TC_555_565_RGB = 41,
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FMT_ATI_TC_555_565_RGBA = 42,
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FMT_ATI_TC_RGBA_INTERP = 43,
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FMT_ATI_TC_555_565_RGBA_INTERP = 44,
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FMT_ETC1_RGBA_INTERP = 46,
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FMT_ETC1_RGB = 47,
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FMT_ETC1_RGBA = 48,
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FMT_DXN = 49,
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FMT_8_8_8_8_AS_16_16_16_16 = 50,
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FMT_DXT1_AS_16_16_16_16 = 51,
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FMT_DXT2_3_AS_16_16_16_16 = 52,
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FMT_DXT4_5_AS_16_16_16_16 = 53,
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FMT_2_3_3 = 51,
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FMT_2_10_10_10_AS_16_16_16_16 = 54,
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FMT_10_11_11_AS_16_16_16_16 = 55,
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FMT_11_11_10_AS_16_16_16_16 = 56,
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FMT_10_10_10_2_AS_16_16_16_16 = 55,
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FMT_32_32_32_FLOAT = 57,
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FMT_DXT3A = 58,
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FMT_DXT5A = 59,
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FMT_CTX1 = 60,
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FMT_DXT3A_AS_1_1_1_1 = 61,
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};
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enum a2xx_sq_ps_vtx_mode {
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@ -8,17 +8,19 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2017 by the following authors:
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Copyright (C) 2013-2018 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@ -8,17 +8,19 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2017 by the following authors:
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Copyright (C) 2013-2018 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@ -263,12 +265,6 @@ enum a4xx_depth_format {
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DEPTH4_32 = 3,
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};
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enum a4xx_tess_spacing {
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EQUAL_SPACING = 0,
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ODD_SPACING = 2,
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EVEN_SPACING = 3,
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};
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enum a4xx_ccu_perfcounter_select {
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CCU_BUSY_CYCLES = 0,
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CCU_RB_DEPTH_RETURN_STALL = 2,
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@ -3544,12 +3540,13 @@ static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3571,12 +3568,13 @@ static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3598,12 +3596,13 @@ static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3625,12 +3624,13 @@ static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3652,12 +3652,13 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
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}
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#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
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#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
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#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
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static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
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{
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return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
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}
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#define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000
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#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
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#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
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#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
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@ -3672,23 +3673,103 @@ static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
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return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
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}
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#define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
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#define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca
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#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
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#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0
|
||||
static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK;
|
||||
}
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
|
||||
static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
|
||||
}
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
|
||||
static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK;
|
||||
}
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
|
||||
#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24
|
||||
static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0
|
||||
static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK;
|
||||
}
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2
|
||||
static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK;
|
||||
}
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12
|
||||
static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK;
|
||||
}
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
|
||||
#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22
|
||||
static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
|
||||
#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff
|
||||
#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0
|
||||
static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
|
||||
#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff
|
||||
#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0
|
||||
static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
|
||||
#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff
|
||||
#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0
|
||||
static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
|
||||
#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff
|
||||
#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
|
||||
static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
|
||||
}
|
||||
#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
|
||||
#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
|
||||
static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
|
||||
|
||||
|
|
@ -4087,5 +4168,71 @@ static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
|
|||
|
||||
#define REG_A4XX_TEX_CONST_7 0x00000007
|
||||
|
||||
#define REG_A4XX_SSBO_0_0 0x00000000
|
||||
#define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0
|
||||
#define A4XX_SSBO_0_0_BASE__SHIFT 5
|
||||
static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
|
||||
{
|
||||
return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_0_1 0x00000001
|
||||
#define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff
|
||||
#define A4XX_SSBO_0_1_PITCH__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_0_2 0x00000002
|
||||
#define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
|
||||
#define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
|
||||
static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
|
||||
{
|
||||
return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_0_3 0x00000003
|
||||
#define A4XX_SSBO_0_3_CPP__MASK 0x0000003f
|
||||
#define A4XX_SSBO_0_3_CPP__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_1_0 0x00000000
|
||||
#define A4XX_SSBO_1_0_CPP__MASK 0x0000001f
|
||||
#define A4XX_SSBO_1_0_CPP__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK;
|
||||
}
|
||||
#define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00
|
||||
#define A4XX_SSBO_1_0_FMT__SHIFT 8
|
||||
static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK;
|
||||
}
|
||||
#define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000
|
||||
#define A4XX_SSBO_1_0_WIDTH__SHIFT 16
|
||||
static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_SSBO_1_1 0x00000001
|
||||
#define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
|
||||
#define A4XX_SSBO_1_1_HEIGHT__SHIFT 0
|
||||
static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK;
|
||||
}
|
||||
#define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000
|
||||
#define A4XX_SSBO_1_1_DEPTH__SHIFT 16
|
||||
static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* A4XX_XML */
|
||||
|
|
|
|||
|
|
@ -8,17 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -119,6 +121,11 @@ enum a5xx_vtx_fmt {
|
|||
VFMT5_8_8_8_8_SNORM = 50,
|
||||
VFMT5_8_8_8_8_UINT = 51,
|
||||
VFMT5_8_8_8_8_SINT = 52,
|
||||
VFMT5_10_10_10_2_UNORM = 54,
|
||||
VFMT5_10_10_10_2_SNORM = 57,
|
||||
VFMT5_10_10_10_2_UINT = 58,
|
||||
VFMT5_10_10_10_2_SINT = 59,
|
||||
VFMT5_11_11_10_FLOAT = 66,
|
||||
VFMT5_16_16_UNORM = 67,
|
||||
VFMT5_16_16_SNORM = 68,
|
||||
VFMT5_16_16_FLOAT = 69,
|
||||
|
|
@ -204,14 +211,45 @@ enum a5xx_tex_fmt {
|
|||
TFMT5_32_32_FLOAT = 103,
|
||||
TFMT5_32_32_UINT = 104,
|
||||
TFMT5_32_32_SINT = 105,
|
||||
TFMT5_32_32_32_UINT = 114,
|
||||
TFMT5_32_32_32_SINT = 115,
|
||||
TFMT5_32_32_32_FLOAT = 116,
|
||||
TFMT5_32_32_32_32_FLOAT = 130,
|
||||
TFMT5_32_32_32_32_UINT = 131,
|
||||
TFMT5_32_32_32_32_SINT = 132,
|
||||
TFMT5_X8Z24_UNORM = 160,
|
||||
TFMT5_ETC2_RG11_UNORM = 171,
|
||||
TFMT5_ETC2_RG11_SNORM = 172,
|
||||
TFMT5_ETC2_R11_UNORM = 173,
|
||||
TFMT5_ETC2_R11_SNORM = 174,
|
||||
TFMT5_ETC1 = 175,
|
||||
TFMT5_ETC2_RGB8 = 176,
|
||||
TFMT5_ETC2_RGBA8 = 177,
|
||||
TFMT5_ETC2_RGB8A1 = 178,
|
||||
TFMT5_DXT1 = 179,
|
||||
TFMT5_DXT3 = 180,
|
||||
TFMT5_DXT5 = 181,
|
||||
TFMT5_RGTC1_UNORM = 183,
|
||||
TFMT5_RGTC1_SNORM = 184,
|
||||
TFMT5_RGTC2_UNORM = 187,
|
||||
TFMT5_RGTC2_SNORM = 188,
|
||||
TFMT5_BPTC_UFLOAT = 190,
|
||||
TFMT5_BPTC_FLOAT = 191,
|
||||
TFMT5_BPTC = 192,
|
||||
TFMT5_ASTC_4x4 = 193,
|
||||
TFMT5_ASTC_5x4 = 194,
|
||||
TFMT5_ASTC_5x5 = 195,
|
||||
TFMT5_ASTC_6x5 = 196,
|
||||
TFMT5_ASTC_6x6 = 197,
|
||||
TFMT5_ASTC_8x5 = 198,
|
||||
TFMT5_ASTC_8x6 = 199,
|
||||
TFMT5_ASTC_8x8 = 200,
|
||||
TFMT5_ASTC_10x5 = 201,
|
||||
TFMT5_ASTC_10x6 = 202,
|
||||
TFMT5_ASTC_10x8 = 203,
|
||||
TFMT5_ASTC_10x10 = 204,
|
||||
TFMT5_ASTC_12x10 = 205,
|
||||
TFMT5_ASTC_12x12 = 206,
|
||||
};
|
||||
|
||||
enum a5xx_tex_fetchsize {
|
||||
|
|
@ -239,7 +277,7 @@ enum a5xx_blit_buf {
|
|||
BLIT_MRT6 = 6,
|
||||
BLIT_MRT7 = 7,
|
||||
BLIT_ZS = 8,
|
||||
BLIT_Z32 = 9,
|
||||
BLIT_S = 9,
|
||||
};
|
||||
|
||||
enum a5xx_cp_perfcounter_select {
|
||||
|
|
@ -899,6 +937,12 @@ enum a5xx_tex_type {
|
|||
|
||||
#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
|
||||
|
||||
#define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d
|
||||
|
||||
#define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e
|
||||
|
||||
#define REG_A5XX_CP_ME_NRT_DATA 0x00000810
|
||||
|
||||
#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
|
||||
|
||||
#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
|
||||
|
|
@ -2072,9 +2116,17 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
|||
|
||||
#define REG_A5XX_PC_MODE_CNTL 0x00000d02
|
||||
|
||||
#define REG_A5XX_UNKNOWN_0D08 0x00000d08
|
||||
#define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04
|
||||
|
||||
#define REG_A5XX_UNKNOWN_0D09 0x00000d09
|
||||
#define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05
|
||||
|
||||
#define REG_A5XX_PC_START_INDEX 0x00000d06
|
||||
|
||||
#define REG_A5XX_PC_MAX_INDEX 0x00000d07
|
||||
|
||||
#define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08
|
||||
|
||||
#define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09
|
||||
|
||||
#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
|
||||
|
||||
|
|
@ -2327,6 +2379,14 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
|||
|
||||
#define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
|
||||
|
||||
#define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8
|
||||
|
||||
#define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c9
|
||||
|
||||
#define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030ca
|
||||
|
||||
#define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030cb
|
||||
|
||||
#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
|
||||
|
||||
#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
|
||||
|
|
@ -2590,6 +2650,7 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
|
|||
#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
|
||||
|
||||
#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
|
||||
#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E001 0x0000e001
|
||||
|
||||
|
|
@ -2700,7 +2761,7 @@ static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
|
|||
return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E093 0x0000e093
|
||||
#define REG_A5XX_GRAS_SU_LAYERED 0x0000e093
|
||||
|
||||
#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
|
||||
#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
|
||||
|
|
@ -2936,7 +2997,9 @@ static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
|
|||
#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
|
||||
|
||||
#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
|
||||
#define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
|
||||
#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
|
||||
#define A5XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000004
|
||||
|
||||
#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
|
||||
#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
|
||||
|
|
@ -3002,6 +3065,13 @@ static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0
|
|||
static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
|
||||
#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
|
||||
#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
|
||||
#define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
|
||||
#define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
|
||||
#define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
|
||||
static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
|
||||
{
|
||||
return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
|
||||
}
|
||||
#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
|
||||
#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
|
||||
static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
|
||||
|
|
@ -3060,6 +3130,12 @@ static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode
|
|||
{
|
||||
return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00001800
|
||||
#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 11
|
||||
static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
|
||||
{
|
||||
return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
|
||||
}
|
||||
#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
|
||||
#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
|
||||
static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
|
|
@ -3223,6 +3299,7 @@ static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
|
|||
return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
|
||||
}
|
||||
#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
|
||||
#define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
|
||||
#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
|
||||
#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
|
||||
|
|
@ -3369,7 +3446,25 @@ static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
|
|||
return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7
|
||||
#define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7
|
||||
#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
|
||||
#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
|
||||
static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
|
||||
}
|
||||
#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
|
||||
#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
|
||||
static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
|
||||
}
|
||||
#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
|
||||
#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
|
||||
static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
|
||||
#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
|
||||
|
|
@ -3428,6 +3523,7 @@ static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
|
||||
#define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001
|
||||
|
||||
#define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
|
||||
|
||||
|
|
@ -3459,6 +3555,7 @@ static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
|
|||
|
||||
#define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
|
||||
#define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
|
||||
#define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE 0x00000004
|
||||
#define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
|
||||
#define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
|
||||
static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
|
||||
|
|
@ -3627,22 +3724,69 @@ static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
|
|||
{
|
||||
return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
|
||||
}
|
||||
#define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100
|
||||
#define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200
|
||||
#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
|
||||
|
||||
#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
|
||||
#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
|
||||
|
||||
#define REG_A5XX_PC_RASTER_CNTL 0x0000e388
|
||||
#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007
|
||||
#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0
|
||||
static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
|
||||
{
|
||||
return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
|
||||
}
|
||||
#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
|
||||
#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
|
||||
static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
|
||||
{
|
||||
return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
|
||||
}
|
||||
#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E389 0x0000e389
|
||||
|
||||
#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E38D 0x0000e38d
|
||||
#define REG_A5XX_PC_GS_LAYERED 0x0000e38d
|
||||
|
||||
#define REG_A5XX_PC_GS_PARAM 0x0000e38e
|
||||
#define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
|
||||
#define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
|
||||
static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
|
||||
}
|
||||
#define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
|
||||
#define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
|
||||
static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
|
||||
}
|
||||
#define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
|
||||
#define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
|
||||
static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
|
||||
{
|
||||
return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_PC_HS_PARAM 0x0000e38f
|
||||
#define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
|
||||
#define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
|
||||
static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
|
||||
}
|
||||
#define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000
|
||||
#define A5XX_PC_HS_PARAM_SPACING__SHIFT 21
|
||||
static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
|
||||
{
|
||||
return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
|
||||
}
|
||||
#define A5XX_PC_HS_PARAM_CW 0x00800000
|
||||
#define A5XX_PC_HS_PARAM_CONNECTED 0x01000000
|
||||
|
||||
#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
|
||||
|
||||
|
|
@ -3667,10 +3811,40 @@ static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
|
|||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
|
||||
}
|
||||
#define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
|
||||
#define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
|
||||
static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VFD_CONTROL_2 0x0000e402
|
||||
#define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
|
||||
#define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
|
||||
static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VFD_CONTROL_3 0x0000e403
|
||||
#define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
|
||||
#define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
|
||||
static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
|
||||
}
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
|
||||
static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
|
||||
}
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
|
||||
#define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
|
||||
static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_VFD_CONTROL_4 0x0000e404
|
||||
|
||||
|
|
@ -3700,12 +3874,18 @@ static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
|
|||
return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
|
||||
}
|
||||
#define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
|
||||
#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000
|
||||
#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
|
||||
#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
|
||||
static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
|
||||
#define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
|
||||
static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
|
||||
#define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
|
||||
|
||||
|
|
@ -3960,6 +4140,7 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|||
#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
|
||||
#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
|
||||
#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
|
||||
#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
|
||||
|
||||
#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
|
||||
#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
|
||||
|
|
@ -4001,16 +4182,12 @@ static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|||
{
|
||||
return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
|
||||
#define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
|
||||
#define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
|
||||
|
||||
#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
|
||||
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
||||
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
|
||||
|
|
@ -4039,7 +4216,39 @@ static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|||
return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E600 0x0000e600
|
||||
#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
|
||||
|
||||
#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
|
||||
|
||||
#define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600
|
||||
#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
||||
#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 3
|
||||
static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
||||
{
|
||||
return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
|
||||
}
|
||||
#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
||||
#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
||||
static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
||||
#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
||||
static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A5XX_SP_HS_CTRL_REG0_VARYING 0x00010000
|
||||
#define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x00100000
|
||||
#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
|
||||
#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 25
|
||||
static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E602 0x0000e602
|
||||
|
||||
|
|
@ -4047,13 +4256,67 @@ static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
|||
|
||||
#define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
|
||||
|
||||
#define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610
|
||||
#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
||||
#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 3
|
||||
static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
||||
{
|
||||
return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
|
||||
}
|
||||
#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
||||
#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
||||
static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
||||
#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
||||
static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A5XX_SP_DS_CTRL_REG0_VARYING 0x00010000
|
||||
#define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x00100000
|
||||
#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
|
||||
#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 25
|
||||
static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E62B 0x0000e62b
|
||||
|
||||
#define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
|
||||
|
||||
#define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E640 0x0000e640
|
||||
#define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640
|
||||
#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008
|
||||
#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 3
|
||||
static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
|
||||
{
|
||||
return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
|
||||
}
|
||||
#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
|
||||
#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
|
||||
static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
|
||||
#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
|
||||
static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
|
||||
}
|
||||
#define A5XX_SP_GS_CTRL_REG0_VARYING 0x00010000
|
||||
#define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x00100000
|
||||
#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
|
||||
#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 25
|
||||
static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_UNKNOWN_E65B 0x0000e65b
|
||||
|
||||
|
|
@ -4173,6 +4436,18 @@ static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
|
|||
{
|
||||
return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
|
||||
}
|
||||
#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
|
||||
#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
|
||||
static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
|
||||
}
|
||||
#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
|
||||
#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
|
||||
static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
|
||||
#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
|
||||
|
|
@ -4375,34 +4650,52 @@ static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
|
||||
#define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val)
|
||||
#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK;
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
|
||||
#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
|
||||
#define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val)
|
||||
#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK;
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
|
||||
#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
|
||||
#define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val)
|
||||
#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK;
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
|
||||
#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
|
||||
#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
|
||||
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
|
||||
#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
|
||||
|
|
@ -4468,6 +4761,8 @@ static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
|
|||
|
||||
#define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
|
||||
|
||||
#define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100
|
||||
|
||||
#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
|
||||
|
||||
#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
|
||||
|
|
@ -4483,12 +4778,19 @@ static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|||
{
|
||||
return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_RB_2D_SRC_LO 0x00002108
|
||||
|
||||
|
|
@ -4515,12 +4817,19 @@ static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
|
|||
{
|
||||
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_RB_2D_DST_LO 0x00002111
|
||||
|
||||
|
|
@ -4548,6 +4857,8 @@ static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
|
|||
|
||||
#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
|
||||
|
||||
#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
|
||||
|
||||
#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
|
||||
|
|
@ -4555,12 +4866,19 @@ static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt va
|
|||
{
|
||||
return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
|
||||
#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
|
||||
|
|
@ -4569,12 +4887,19 @@ static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt va
|
|||
{
|
||||
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300
|
||||
#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8
|
||||
static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
|
||||
#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
|
||||
static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
|
||||
{
|
||||
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
|
||||
}
|
||||
#define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000
|
||||
|
||||
#define REG_A5XX_UNKNOWN_2100 0x00002100
|
||||
|
||||
|
|
@ -4698,6 +5023,12 @@ static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
|
|||
{
|
||||
return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
|
||||
}
|
||||
#define A5XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
|
||||
#define A5XX_TEX_CONST_0_SAMPLES__SHIFT 20
|
||||
static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
|
||||
{
|
||||
return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK;
|
||||
}
|
||||
#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
|
||||
#define A5XX_TEX_CONST_0_FMT__SHIFT 22
|
||||
static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
|
||||
|
|
@ -4788,5 +5119,81 @@ static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
|
|||
|
||||
#define REG_A5XX_TEX_CONST_11 0x0000000b
|
||||
|
||||
#define REG_A5XX_SSBO_0_0 0x00000000
|
||||
#define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0
|
||||
#define A5XX_SSBO_0_0_BASE_LO__SHIFT 5
|
||||
static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
|
||||
{
|
||||
return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_SSBO_0_1 0x00000001
|
||||
#define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff
|
||||
#define A5XX_SSBO_0_1_PITCH__SHIFT 0
|
||||
static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_SSBO_0_2 0x00000002
|
||||
#define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
|
||||
#define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
|
||||
static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
|
||||
{
|
||||
return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_SSBO_0_3 0x00000003
|
||||
#define A5XX_SSBO_0_3_CPP__MASK 0x0000003f
|
||||
#define A5XX_SSBO_0_3_CPP__SHIFT 0
|
||||
static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_SSBO_1_0 0x00000000
|
||||
#define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00
|
||||
#define A5XX_SSBO_1_0_FMT__SHIFT 8
|
||||
static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
|
||||
}
|
||||
#define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000
|
||||
#define A5XX_SSBO_1_0_WIDTH__SHIFT 16
|
||||
static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_SSBO_1_1 0x00000001
|
||||
#define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
|
||||
#define A5XX_SSBO_1_1_HEIGHT__SHIFT 0
|
||||
static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
|
||||
}
|
||||
#define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000
|
||||
#define A5XX_SSBO_1_1_DEPTH__SHIFT 16
|
||||
static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_SSBO_2_0 0x00000000
|
||||
#define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff
|
||||
#define A5XX_SSBO_2_0_BASE_LO__SHIFT 0
|
||||
static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_SSBO_2_1 0x00000001
|
||||
#define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff
|
||||
#define A5XX_SSBO_2_1_BASE_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* A5XX_XML */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,382 @@
|
|||
#ifndef A6XX_GMU_XML
|
||||
#define A6XX_GMU_XML
|
||||
|
||||
/* Autogenerated file, DO NOT EDIT manually!
|
||||
|
||||
This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000
|
||||
#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000
|
||||
#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000
|
||||
#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000
|
||||
#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000
|
||||
#define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000
|
||||
#define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000
|
||||
#define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000
|
||||
#define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000
|
||||
#define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000
|
||||
#define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000
|
||||
#define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000
|
||||
#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000
|
||||
#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000
|
||||
#define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001
|
||||
#define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002
|
||||
#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004
|
||||
#define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000
|
||||
#define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000
|
||||
#define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16
|
||||
static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK;
|
||||
}
|
||||
#define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000
|
||||
#define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24
|
||||
static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK;
|
||||
}
|
||||
#define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001
|
||||
#define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080
|
||||
|
||||
#define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081
|
||||
|
||||
#define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00
|
||||
|
||||
#define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00
|
||||
|
||||
#define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0
|
||||
|
||||
#define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8
|
||||
|
||||
#define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9
|
||||
|
||||
#define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa
|
||||
|
||||
#define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc
|
||||
|
||||
#define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd
|
||||
|
||||
#define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe
|
||||
|
||||
#define REG_A6XX_GMU_DCVS_RETURN 0x000023ff
|
||||
|
||||
#define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f
|
||||
|
||||
#define REG_A6XX_GMU_CM3_SYSRESET 0x00005000
|
||||
|
||||
#define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001
|
||||
|
||||
#define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a
|
||||
|
||||
#define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c
|
||||
|
||||
#define REG_A6XX_GMU_CM3_CFG 0x0000502d
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e
|
||||
|
||||
#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f
|
||||
|
||||
#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0
|
||||
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001
|
||||
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002
|
||||
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004
|
||||
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00
|
||||
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10
|
||||
static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val)
|
||||
{
|
||||
return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK;
|
||||
}
|
||||
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000
|
||||
#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14
|
||||
static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1
|
||||
|
||||
#define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2
|
||||
|
||||
#define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000004
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000008
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040
|
||||
#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080
|
||||
|
||||
#define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4
|
||||
#define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001
|
||||
#define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0
|
||||
#define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4
|
||||
static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
|
||||
{
|
||||
return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK;
|
||||
}
|
||||
|
||||
#define REG_A6XX_GMU_RPMH_CTRL 0x000050e8
|
||||
#define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001
|
||||
#define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010
|
||||
#define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100
|
||||
#define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200
|
||||
#define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400
|
||||
#define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800
|
||||
#define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000
|
||||
#define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000
|
||||
#define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000
|
||||
#define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000
|
||||
|
||||
#define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9
|
||||
|
||||
#define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec
|
||||
|
||||
#define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0
|
||||
|
||||
#define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157
|
||||
|
||||
#define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158
|
||||
|
||||
#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088
|
||||
|
||||
#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089
|
||||
|
||||
#define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3
|
||||
|
||||
#define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180
|
||||
|
||||
#define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181
|
||||
|
||||
#define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182
|
||||
|
||||
#define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183
|
||||
|
||||
#define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184
|
||||
|
||||
#define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185
|
||||
|
||||
#define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186
|
||||
|
||||
#define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190
|
||||
|
||||
#define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191
|
||||
|
||||
#define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192
|
||||
#define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001
|
||||
#define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000
|
||||
|
||||
#define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d
|
||||
|
||||
#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e
|
||||
|
||||
#define REG_A6XX_GMU_GENERAL_1 0x000051c6
|
||||
|
||||
#define REG_A6XX_GMU_GENERAL_7 0x000051cc
|
||||
|
||||
#define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
|
||||
|
||||
#define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920
|
||||
|
||||
#define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558
|
||||
|
||||
#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580
|
||||
|
||||
#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada
|
||||
|
||||
#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957
|
||||
|
||||
#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d
|
||||
|
||||
#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
|
||||
|
||||
#define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d
|
||||
|
||||
#define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303
|
||||
|
||||
#define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304
|
||||
|
||||
#define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305
|
||||
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001
|
||||
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002
|
||||
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004
|
||||
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008
|
||||
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010
|
||||
#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020
|
||||
|
||||
#define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306
|
||||
|
||||
#define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309
|
||||
|
||||
#define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a
|
||||
|
||||
#define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b
|
||||
|
||||
#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c
|
||||
#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000
|
||||
|
||||
#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d
|
||||
|
||||
#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e
|
||||
|
||||
#define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310
|
||||
|
||||
#define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313
|
||||
|
||||
#define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315
|
||||
|
||||
#define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
|
||||
|
||||
#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00008c04
|
||||
|
||||
#define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307
|
||||
|
||||
#define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308
|
||||
|
||||
#define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311
|
||||
|
||||
#define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312
|
||||
|
||||
#define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03
|
||||
|
||||
#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
|
||||
|
||||
#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00008c08
|
||||
|
||||
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00008c09
|
||||
|
||||
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x00008c0a
|
||||
|
||||
#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x00008c0b
|
||||
|
||||
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x00008c0d
|
||||
|
||||
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x00008c0e
|
||||
|
||||
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00008c82
|
||||
|
||||
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00008c83
|
||||
|
||||
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00008c89
|
||||
|
||||
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x00008c8c
|
||||
|
||||
#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00008d00
|
||||
|
||||
#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00008d01
|
||||
|
||||
#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00008d80
|
||||
|
||||
#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00008f46
|
||||
|
||||
#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000090ae
|
||||
|
||||
#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00009216
|
||||
|
||||
#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000937e
|
||||
|
||||
|
||||
#endif /* A6XX_GMU_XML */
|
||||
|
|
@ -8,17 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -44,6 +46,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|||
*/
|
||||
|
||||
|
||||
enum chip {
|
||||
A2XX = 0,
|
||||
A3XX = 0,
|
||||
A4XX = 0,
|
||||
A5XX = 0,
|
||||
A6XX = 0,
|
||||
};
|
||||
|
||||
enum adreno_pa_su_sc_draw {
|
||||
PC_DRAW_POINTS = 0,
|
||||
PC_DRAW_LINES = 1,
|
||||
|
|
@ -181,6 +191,12 @@ enum a3xx_rb_blend_opcode {
|
|||
BLEND_MAX_DST_SRC = 4,
|
||||
};
|
||||
|
||||
enum a4xx_tess_spacing {
|
||||
EQUAL_SPACING = 0,
|
||||
ODD_SPACING = 2,
|
||||
EVEN_SPACING = 3,
|
||||
};
|
||||
|
||||
#define REG_AXXX_CP_RB_BASE 0x000001c0
|
||||
|
||||
#define REG_AXXX_CP_RB_CNTL 0x000001c1
|
||||
|
|
|
|||
|
|
@ -8,17 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -71,7 +73,8 @@ enum vgt_event_type {
|
|||
FLUSH_SO_1 = 18,
|
||||
FLUSH_SO_2 = 19,
|
||||
FLUSH_SO_3 = 20,
|
||||
UNK_19 = 25,
|
||||
PC_CCU_INVALIDATE_DEPTH = 24,
|
||||
PC_CCU_INVALIDATE_COLOR = 25,
|
||||
UNK_1C = 28,
|
||||
UNK_1D = 29,
|
||||
BLIT = 30,
|
||||
|
|
@ -199,9 +202,12 @@ enum adreno_pm4_type3_packets {
|
|||
CP_WAIT_MEM_WRITES = 18,
|
||||
CP_COND_REG_EXEC = 71,
|
||||
CP_MEM_TO_REG = 66,
|
||||
CP_EXEC_CS_INDIRECT = 65,
|
||||
CP_EXEC_CS = 51,
|
||||
CP_PERFCOUNTER_ACTION = 80,
|
||||
CP_SMMU_TABLE_UPDATE = 83,
|
||||
CP_SET_MARKER = 101,
|
||||
CP_SET_PSEUDO_REG = 86,
|
||||
CP_CONTEXT_REG_BUNCH = 92,
|
||||
CP_YIELD_ENABLE = 28,
|
||||
CP_SKIP_IB2_ENABLE_GLOBAL = 29,
|
||||
|
|
@ -215,7 +221,10 @@ enum adreno_pm4_type3_packets {
|
|||
CP_COMPUTE_CHECKPOINT = 110,
|
||||
CP_MEM_TO_MEM = 115,
|
||||
CP_BLIT = 44,
|
||||
CP_UNK_39 = 57,
|
||||
CP_REG_TEST = 57,
|
||||
CP_SET_MODE = 99,
|
||||
CP_LOAD_STATE6_GEOM = 50,
|
||||
CP_LOAD_STATE6_FRAG = 52,
|
||||
IN_IB_PREFETCH_END = 23,
|
||||
IN_SUBBLK_PREFETCH = 31,
|
||||
IN_INSTR_PREFETCH = 32,
|
||||
|
|
@ -224,6 +233,11 @@ enum adreno_pm4_type3_packets {
|
|||
IN_INCR_UPDT_STATE = 85,
|
||||
IN_INCR_UPDT_CONST = 86,
|
||||
IN_INCR_UPDT_INSTR = 87,
|
||||
PKT4 = 4,
|
||||
CP_UNK_A6XX_14 = 20,
|
||||
CP_UNK_A6XX_36 = 54,
|
||||
CP_UNK_A6XX_55 = 85,
|
||||
UNK_A6XX_6D = 109,
|
||||
};
|
||||
|
||||
enum adreno_state_block {
|
||||
|
|
@ -278,6 +292,33 @@ enum a4xx_state_src {
|
|||
SS4_INDIRECT = 2,
|
||||
};
|
||||
|
||||
enum a6xx_state_block {
|
||||
SB6_VS_TEX = 0,
|
||||
SB6_HS_TEX = 1,
|
||||
SB6_DS_TEX = 2,
|
||||
SB6_GS_TEX = 3,
|
||||
SB6_FS_TEX = 4,
|
||||
SB6_CS_TEX = 5,
|
||||
SB6_VS_SHADER = 8,
|
||||
SB6_HS_SHADER = 9,
|
||||
SB6_DS_SHADER = 10,
|
||||
SB6_GS_SHADER = 11,
|
||||
SB6_FS_SHADER = 12,
|
||||
SB6_CS_SHADER = 13,
|
||||
SB6_SSBO = 14,
|
||||
SB6_CS_SSBO = 15,
|
||||
};
|
||||
|
||||
enum a6xx_state_type {
|
||||
ST6_SHADER = 0,
|
||||
ST6_CONSTANTS = 1,
|
||||
};
|
||||
|
||||
enum a6xx_state_src {
|
||||
SS6_DIRECT = 0,
|
||||
SS6_INDIRECT = 2,
|
||||
};
|
||||
|
||||
enum a4xx_index_size {
|
||||
INDEX4_SIZE_8_BIT = 0,
|
||||
INDEX4_SIZE_16_BIT = 1,
|
||||
|
|
@ -300,6 +341,7 @@ enum render_mode_cmd {
|
|||
GMEM = 3,
|
||||
BLIT2D = 5,
|
||||
BLIT2DSCALE = 7,
|
||||
END2D = 8,
|
||||
};
|
||||
|
||||
enum cp_blit_cmd {
|
||||
|
|
@ -308,6 +350,22 @@ enum cp_blit_cmd {
|
|||
BLIT_OP_SCALE = 3,
|
||||
};
|
||||
|
||||
enum a6xx_render_mode {
|
||||
RM6_BYPASS = 1,
|
||||
RM6_BINNING = 2,
|
||||
RM6_GMEM = 4,
|
||||
RM6_BLIT2D = 5,
|
||||
RM6_RESOLVE = 6,
|
||||
};
|
||||
|
||||
enum pseudo_reg {
|
||||
SMMU_INFO = 0,
|
||||
NON_SECURE_SAVE_ADDR = 1,
|
||||
SECURE_SAVE_ADDR = 2,
|
||||
NON_PRIV_SAVE_ADDR = 3,
|
||||
COUNTER = 4,
|
||||
};
|
||||
|
||||
#define REG_CP_LOAD_STATE_0 0x00000000
|
||||
#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
|
||||
#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
|
||||
|
|
@ -349,7 +407,7 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE4_0 0x00000000
|
||||
#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x0000ffff
|
||||
#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
|
||||
#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
|
||||
{
|
||||
|
|
@ -396,6 +454,54 @@ static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
|
|||
return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE6_0 0x00000000
|
||||
#define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
|
||||
#define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x00004000
|
||||
#define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
|
||||
static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
|
||||
#define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
|
||||
static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
|
||||
#define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
|
||||
static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
|
||||
#define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
|
||||
static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE6_1 0x00000001
|
||||
#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
|
||||
#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
|
||||
static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE6_2 0x00000002
|
||||
#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_0 0x00000000
|
||||
#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
|
||||
#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
|
||||
|
|
@ -580,6 +686,153 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
|
|||
return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
|
||||
static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
|
||||
static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
|
||||
static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
|
||||
#define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
|
||||
static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
|
||||
#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
|
||||
#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
|
||||
}
|
||||
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
|
||||
#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
|
||||
}
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
|
||||
}
|
||||
|
||||
|
||||
#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
|
||||
#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
|
||||
}
|
||||
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
|
||||
#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
||||
|
||||
static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
||||
|
|
@ -593,6 +846,12 @@ static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
|
|||
#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
|
||||
#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
|
||||
#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
|
||||
#define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000
|
||||
#define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20
|
||||
static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;
|
||||
}
|
||||
#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
|
||||
#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
|
||||
static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
|
||||
|
|
@ -708,6 +967,22 @@ static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
|
|||
return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_5 0x00000005
|
||||
#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_5_XXX_ADDRESS_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_6 0x00000006
|
||||
#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_6_XXX_ADDRESS_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_0 0x00000000
|
||||
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
|
||||
#define CP_REG_TO_MEM_0_REG__SHIFT 0
|
||||
|
|
@ -732,6 +1007,46 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
|
|||
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_2 0x00000002
|
||||
#define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
|
||||
#define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
|
||||
static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_MEM_TO_REG_0 0x00000000
|
||||
#define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff
|
||||
#define CP_MEM_TO_REG_0_REG__SHIFT 0
|
||||
static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
|
||||
}
|
||||
#define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
|
||||
#define CP_MEM_TO_REG_0_CNT__SHIFT 19
|
||||
static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
|
||||
}
|
||||
#define CP_MEM_TO_REG_0_64B 0x40000000
|
||||
#define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000
|
||||
|
||||
#define REG_CP_MEM_TO_REG_1 0x00000001
|
||||
#define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
|
||||
#define CP_MEM_TO_REG_1_SRC__SHIFT 0
|
||||
static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_MEM_TO_REG_2 0x00000002
|
||||
#define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
|
||||
#define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
|
||||
static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_MEM_TO_MEM_0 0x00000000
|
||||
#define CP_MEM_TO_MEM_0_NEG_A 0x00000001
|
||||
#define CP_MEM_TO_MEM_0_NEG_B 0x00000002
|
||||
|
|
@ -953,14 +1268,14 @@ static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
|
|||
#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
|
||||
#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
|
||||
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
|
||||
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
|
||||
|
|
@ -978,6 +1293,8 @@ static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
|
|||
return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
|
||||
|
||||
#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
|
||||
|
||||
#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
|
||||
|
|
@ -1032,13 +1349,13 @@ static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_1 0x00000001
|
||||
#define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
|
||||
#define CP_BLIT_1_SRC_X1__MASK 0x00003fff
|
||||
#define CP_BLIT_1_SRC_X1__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
|
||||
}
|
||||
#define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
|
||||
#define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
|
||||
#define CP_BLIT_1_SRC_Y1__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
|
||||
{
|
||||
|
|
@ -1046,13 +1363,13 @@ static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_2 0x00000002
|
||||
#define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
|
||||
#define CP_BLIT_2_SRC_X2__MASK 0x00003fff
|
||||
#define CP_BLIT_2_SRC_X2__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
|
||||
}
|
||||
#define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
|
||||
#define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
|
||||
#define CP_BLIT_2_SRC_Y2__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
|
||||
{
|
||||
|
|
@ -1060,13 +1377,13 @@ static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_3 0x00000003
|
||||
#define CP_BLIT_3_DST_X1__MASK 0x0000ffff
|
||||
#define CP_BLIT_3_DST_X1__MASK 0x00003fff
|
||||
#define CP_BLIT_3_DST_X1__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
|
||||
}
|
||||
#define CP_BLIT_3_DST_Y1__MASK 0xffff0000
|
||||
#define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
|
||||
#define CP_BLIT_3_DST_Y1__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
|
||||
{
|
||||
|
|
@ -1074,13 +1391,13 @@ static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_BLIT_4 0x00000004
|
||||
#define CP_BLIT_4_DST_X2__MASK 0x0000ffff
|
||||
#define CP_BLIT_4_DST_X2__MASK 0x00003fff
|
||||
#define CP_BLIT_4_DST_X2__SHIFT 0
|
||||
static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
|
||||
}
|
||||
#define CP_BLIT_4_DST_Y2__MASK 0xffff0000
|
||||
#define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
|
||||
#define CP_BLIT_4_DST_Y2__SHIFT 16
|
||||
static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
|
||||
{
|
||||
|
|
@ -1113,5 +1430,129 @@ static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
|
|||
return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
|
||||
|
||||
|
||||
#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
|
||||
}
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
|
||||
}
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
|
||||
#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
|
||||
static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
|
||||
{
|
||||
return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
|
||||
}
|
||||
|
||||
|
||||
#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
|
||||
}
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
|
||||
}
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
|
||||
#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
|
||||
static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
|
||||
{
|
||||
return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_CP_SET_MARKER_0 0x00000000
|
||||
#define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
|
||||
#define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0
|
||||
static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;
|
||||
}
|
||||
#define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f
|
||||
#define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0
|
||||
static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
|
||||
{
|
||||
return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;
|
||||
}
|
||||
#define A2XX_CP_SET_MARKER_0_IFPC 0x00000100
|
||||
|
||||
static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
||||
|
||||
static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
|
||||
#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
|
||||
#define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
|
||||
static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
|
||||
{
|
||||
return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
|
||||
#define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
|
||||
#define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
|
||||
static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
|
||||
#define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
|
||||
#define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
|
||||
static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_CP_REG_TEST_0 0x00000000
|
||||
#define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff
|
||||
#define A2XX_CP_REG_TEST_0_REG__SHIFT 0
|
||||
static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;
|
||||
}
|
||||
#define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
|
||||
#define A2XX_CP_REG_TEST_0_BIT__SHIFT 20
|
||||
static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;
|
||||
}
|
||||
#define A2XX_CP_REG_TEST_0_UNK25 0x02000000
|
||||
|
||||
|
||||
#endif /* ADRENO_PM4_XML */
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,8 +8,17 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-01-12 09:09:22)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
|
||||
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
Copyright (C) 2013-2018 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue