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dmaengine: dw: introduce block2bytes() and bytes2block() 

The newly introduced helpers prepare driver to support new DMA controller
hardware.

While here, introduce DWC_CTLH_BLOCK_TS() macro as well.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Andy Shevchenko 2017-01-17 13:57:29 +02:00 committed by Vinod Koul
parent f4aa3183c3
commit 2d248812aa
2 changed files with 35 additions and 23 deletions
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52
drivers/dma/dw/core.c
View File

@ -184,6 +184,27 @@ static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
cpu_relax();
}
static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes,
unsigned int width, size_t *len)
{
u32 block;
if ((bytes >> width) > dwc->block_size) {
block = dwc->block_size;
*len = block << width;
} else {
block = bytes >> width;
*len = bytes;
}
return block;
}
static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
{
return DWC_CTLH_BLOCK_TS(block) << width;
}
/*----------------------------------------------------------------------*/
/* Perform single block transfer */
@ -332,7 +353,7 @@ static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
u32 ctlhi = channel_readl(dwc, CTL_HI);
u32 ctllo = channel_readl(dwc, CTL_LO);
return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
return block2bytes(dwc, ctlhi, ctllo >> 4 & 7);
}
static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
@ -692,10 +713,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
| DWC_CTLL_FC_M2M;
prev = first = NULL;
for (offset = 0; offset < len; offset += xfer_count << src_width) {
xfer_count = min_t(size_t, (len - offset) >> src_width,
dwc->block_size);
for (offset = 0; offset < len; offset += xfer_count) {
desc = dwc_desc_get(dwc);
if (!desc)
goto err_desc_get;
@ -703,8 +721,8 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
lli_write(desc, sar, src + offset);
lli_write(desc, dar, dest + offset);
lli_write(desc, ctllo, ctllo);
lli_write(desc, ctlhi, xfer_count);
desc->len = xfer_count << src_width;
lli_write(desc, ctlhi, bytes2block(dwc, len - offset, src_width, &xfer_count));
desc->len = xfer_count;
if (!first) {
first = desc;
@ -775,7 +793,8 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
for_each_sg(sgl, sg, sg_len, i) {
struct dw_desc *desc;
u32 len, dlen, mem;
u32 len, mem;
size_t dlen;
mem = sg_dma_address(sg);
len = sg_dma_len(sg);
@ -789,12 +808,7 @@ slave_sg_todev_fill_desc:
lli_write(desc, sar, mem);
lli_write(desc, dar, reg);
if ((len >> mem_width) > dwc->block_size) {
dlen = dwc->block_size << mem_width;
} else {
dlen = len;
}
lli_write(desc, ctlhi, dlen >> mem_width);
lli_write(desc, ctlhi, bytes2block(dwc, len, mem_width, &dlen));
lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width));
desc->len = dlen;
@ -827,7 +841,8 @@ slave_sg_todev_fill_desc:
for_each_sg(sgl, sg, sg_len, i) {
struct dw_desc *desc;
u32 len, dlen, mem;
u32 len, mem;
size_t dlen;
mem = sg_dma_address(sg);
len = sg_dma_len(sg);
@ -839,12 +854,7 @@ slave_sg_fromdev_fill_desc:
lli_write(desc, sar, reg);
lli_write(desc, dar, mem);
if ((len >> reg_width) > dwc->block_size) {
dlen = dwc->block_size << reg_width;
} else {
dlen = len;
}
lli_write(desc, ctlhi, dlen >> reg_width);
lli_write(desc, ctlhi, bytes2block(dwc, len, reg_width, &dlen));
mem_width = __ffs(data_width | mem | dlen);
lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width));
desc->len = dlen;

6
drivers/dma/dw/regs.h
View File

@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*/
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>
@ -170,8 +171,9 @@ enum dw_dma_msize {
#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
/* Bitfields in CTL_HI */
#define DWC_CTLH_DONE 0x00001000
#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
#define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0)
#define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK)
#define DWC_CTLH_DONE (1 << 12)
/* Bitfields in CFG_LO */
#define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */