SoCFPGA DTS updates for v4.11, part 1
- Adds FPGA manager bits - Enable I2C on Cyclone5 and Arria5 devkits - Adds LED support on C5/A5 devkits - Enables CAN on C5 devkit - Enables watchdog - Add NAND on Arria10 - Add the LTC2977 Power Monitor on Arria10 devkit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYdlGPAAoJEBmUBAuBoyj0lw0QAIbaW9pIooV/DLFcI0K4wjsq CJhbH1f0f9KGhpKqCdr2J5zToHibb06O6xT+h6799oi1MxnbfGPLD/zjcJ3Jr+kw 2CQc8B9j5zSAeg4DpAMpPPzsUk2XJpIz2rNzI55KRuUYllvFlvQ9mAc1sfbVcPub TBp653uFV3+XKTZz+OZ3zO86bcWGEh8bB0YVqzVArlnoA9PhiWQhV0Ee/cau2VO3 J2GgUmprLVWgOG86OI+WWqEI2Ywc8EAkOXo3DslqoA1zLA4C8ckph3hKiEhjEn+L Bc4EagXbdalXtbqEIFYcKksW8ZrLX2rY9volGUEHFRBYPUmVH32bl5Q+cr/3gBPe 7TtEh6j9uiSvYtCkNalnVfBBGxLr5lalRDkBXiabFhBv2r3iFdpmfmvGhuNptjls QNLqEkVVV3bRxSlmRlr7Jb5PdjlOt8lcqyF2jYxU4JlAD6zotEW3dVWLBG+i6awD n3HUC3FH9DMCxsM5NxhngUYLI8ko7RNpISArApxdEplzxVO1B/+07kzi/JyEMmyI 4DVKUrivpSXUpwsK8GDvmWjXogK1q/ZCzX28zpwRS23a9syJ1f3qm/golyDzQPR4 97RBJWmBqt3Mb2/J8ZO0ybbBkUGFpC2B6HVs+88mHUWJrWU8CV1N7zVrZ7/UVZAf 8zMFRqb/m90Pc7jlNkZB =hbau -----END PGP SIGNATURE----- Merge tag 'socfpga_dts_for_v4.11_part_1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA DTS updates for v4.11, part 1 - Adds FPGA manager bits - Enable I2C on Cyclone5 and Arria5 devkits - Adds LED support on C5/A5 devkits - Enables CAN on C5 devkit - Enables watchdog - Add NAND on Arria10 - Add the LTC2977 Power Monitor on Arria10 devkit * tag 'socfpga_dts_for_v4.11_part_1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: add missing compatible string for SDRAM controller ARM: dts: socfpga: add fpga region support on Arria10 ARM: dts: socfpga: add base fpga region and fpga bridges ARM: dts: socfpga: fpga manager data is 32 bits ARM: dts: socfpga: Add NAND device tree for Arria10 ARM: dts: socfpga: add fpga-manager node for Arria10 ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10 ARM: dts: socfpga: enable CAN on Cyclone5 devkit ARM: dts: socfpga: Add Rohm DH2228FV DAC ARM: dts: socfpga: set desired i2c clock on Cyclone5 and Arria5 devkits ARM: dts: socfpga: enable GPIO and LEDs for Cyclone5 and Arria5 devkits Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
2d19d35c83
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@ -718,6 +718,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
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sh73a0-kzm9g.dtb
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dtb-$(CONFIG_ARCH_SOCFPGA) += \
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socfpga_arria5_socdk.dtb \
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socfpga_arria10_socdk_nand.dtb \
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socfpga_arria10_socdk_qspi.dtb \
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socfpga_arria10_socdk_sdmmc.dtb \
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socfpga_cyclone5_mcvevk.dtb \
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@ -93,6 +93,14 @@
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};
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};
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base_fpga_region {
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compatible = "fpga-region";
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fpga-mgr = <&fpgamgr0>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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};
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can0: can@ffc00000 {
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compatible = "bosch,d_can";
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reg = <0xffc00000 0x1000>;
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@ -513,10 +521,24 @@
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};
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};
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fpga_bridge0: fpga_bridge@ff400000 {
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compatible = "altr,socfpga-lwhps2fpga-bridge";
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reg = <0xff400000 0x100000>;
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resets = <&rst LWHPS2FPGA_RESET>;
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clocks = <&l4_main_clk>;
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};
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fpga_bridge1: fpga_bridge@ff500000 {
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compatible = "altr,socfpga-hps2fpga-bridge";
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reg = <0xff500000 0x10000>;
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resets = <&rst HPS2FPGA_RESET>;
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clocks = <&l4_main_clk>;
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};
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fpgamgr0: fpgamgr@ff706000 {
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compatible = "altr,socfpga-fpga-mgr";
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reg = <0xff706000 0x1000
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0xffb90000 0x1000>;
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0xffb90000 0x4>;
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interrupts = <0 175 4>;
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};
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@ -694,6 +716,11 @@
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arm,prefetch-offset = <7>;
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};
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l3regs@0xff800000 {
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compatible = "altr,l3regs", "syscon";
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reg = <0xff800000 0x1000>;
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};
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mmc: dwmmc0@ff704000 {
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xff704000 0x1000>;
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@ -751,7 +778,7 @@
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};
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sdr: sdr@ffc25000 {
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compatible = "syscon";
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compatible = "altr,sdr-ctl", "syscon";
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reg = <0xffc25000 0x1000>;
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};
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@ -83,6 +83,14 @@
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};
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};
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base_fpga_region {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "fpga-region";
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fpga-mgr = <&fpga_mgr>;
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};
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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@ -512,6 +520,15 @@
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};
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};
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fpga_mgr: fpga-mgr@ffd03000 {
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compatible = "altr,socfpga-a10-fpga-mgr";
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reg = <0xffd03000 0x100
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0xffcfe400 0x20>;
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clocks = <&l4_mp_clk>;
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resets = <&rst FPGAMGR_RESET>;
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reset-names = "fpgamgr";
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};
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i2c0: i2c@ffc02200 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -578,7 +595,7 @@
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};
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sdr: sdr@ffc25000 {
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compatible = "syscon";
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compatible = "altr,sdr-ctl", "syscon";
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reg = <0xffcfb100 0x80>;
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};
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@ -605,6 +622,19 @@
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status = "disabled";
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};
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nand: nand@ffb90000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
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reg = <0xffb90000 0x72000>,
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<0xffb80000 0x10000>;
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reg-names = "nand_data", "denali_reg";
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interrupts = <0 99 4>;
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dma-mask = <0xffffffff>;
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clocks = <&nand_clk>;
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status = "disabled";
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};
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ocram: sram@ffe00000 {
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compatible = "mmio-sram";
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reg = <0xffe00000 0x40000>;
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@ -145,6 +145,11 @@
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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ltc@5c {
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compatible = "ltc2977";
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reg = <0x5c>;
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};
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};
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&uart1 {
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@ -154,3 +159,7 @@
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&usb0 {
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status = "okay";
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};
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&watchdog0 {
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status = "okay";
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};
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@ -0,0 +1,31 @@
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/*
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* Copyright (C) 2015 Altera Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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#include "socfpga_arria10_socdk.dtsi"
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&nand {
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status = "okay";
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partition@nand-boot {
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label = "Boot and fpga data";
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reg = <0x0 0x1C00000>;
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};
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partition@nand-rootfs {
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label = "Root Filesystem - JFFS2";
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reg = <0x1C00000 0x6400000>;
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};
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};
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@ -42,3 +42,7 @@
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};
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};
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};
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&watchdog0 {
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status = "okay";
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};
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@ -39,6 +39,29 @@
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ethernet0 = &gmac1;
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};
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leds {
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compatible = "gpio-leds";
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hps0 {
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label = "hps_led0";
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gpios = <&porta 0 1>;
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};
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hps1 {
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label = "hps_led1";
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gpios = <&portb 11 1>;
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};
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hps2 {
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label = "hps_led2";
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gpios = <&porta 17 1>;
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};
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hps3 {
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label = "hps_led3";
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gpios = <&porta 18 1>;
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};
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};
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regulator_3_3v: 3-3-v-regulator {
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compatible = "regulator-fixed";
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regulator-name = "3.3V";
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@ -61,8 +84,28 @@
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rxc-skew-ps = <2000>;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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/*
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* adjust the falling times to decrease the i2c frequency to 50Khz
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* because the LCD module does not work at the standard 100Khz
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*/
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i2c-sda-falling-time-ns = <5000>;
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i2c-scl-falling-time-ns = <5000>;
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eeprom@51 {
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compatible = "atmel,24c32";
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@ -39,6 +39,29 @@
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ethernet0 = &gmac1;
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};
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leds {
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compatible = "gpio-leds";
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hps0 {
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label = "hps_led0";
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gpios = <&portb 15 1>;
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};
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hps1 {
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label = "hps_led1";
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gpios = <&portb 14 1>;
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};
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hps2 {
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label = "hps_led2";
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gpios = <&portb 13 1>;
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};
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hps3 {
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label = "hps_led3";
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gpios = <&portb 12 1>;
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};
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};
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regulator_3_3v: 3-3-v-regulator {
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compatible = "regulator-fixed";
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regulator-name = "3.3V";
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@ -47,6 +70,10 @@
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};
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};
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&can0 {
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status = "okay";
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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@ -61,12 +88,28 @@
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rxc-skew-ps = <2000>;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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/*
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* adjust the falling times to decrease the i2c frequency to 50Khz
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* because the LCD module does not work at the standard 100Khz
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*/
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i2c-sda-falling-time-ns = <5000>;
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i2c-scl-falling-time-ns = <5000>;
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eeprom@51 {
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compatible = "atmel,24c32";
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@ -120,6 +163,16 @@
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};
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};
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&spi0 {
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status = "okay";
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spidev@0 {
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compatible = "rohm,dh2228fv";
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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};
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&usb1 {
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status = "okay";
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};
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