drm/i915/selftests: Exercise long preemption chains
Verify that we can execute a long chain of dependent requests from userspace, each one slightly more important than the last. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191114225736.616885-4-chris@chris-wilson.co.uk
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@ -1915,6 +1915,201 @@ err_wedged:
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goto err_client_lo;
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}
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static int create_gang(struct intel_engine_cs *engine,
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struct i915_request **prev)
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{
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struct drm_i915_gem_object *obj;
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struct intel_context *ce;
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struct i915_request *rq;
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struct i915_vma *vma;
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u32 *cs;
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int err;
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ce = intel_context_create(engine->kernel_context->gem_context, engine);
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if (IS_ERR(ce))
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return PTR_ERR(ce);
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obj = i915_gem_object_create_internal(engine->i915, 4096);
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if (IS_ERR(obj)) {
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err = PTR_ERR(obj);
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goto err_ce;
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}
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vma = i915_vma_instance(obj, ce->vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_obj;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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goto err_obj;
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cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
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if (IS_ERR(cs))
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goto err_obj;
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/* Semaphore target: spin until zero */
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*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
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*cs++ = MI_SEMAPHORE_WAIT |
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MI_SEMAPHORE_POLL |
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MI_SEMAPHORE_SAD_EQ_SDD;
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*cs++ = 0;
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*cs++ = lower_32_bits(vma->node.start);
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*cs++ = upper_32_bits(vma->node.start);
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if (*prev) {
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u64 offset = (*prev)->batch->node.start;
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/* Terminate the spinner in the next lower priority batch. */
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*cs++ = MI_STORE_DWORD_IMM_GEN4;
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*cs++ = lower_32_bits(offset);
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*cs++ = upper_32_bits(offset);
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*cs++ = 0;
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}
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*cs++ = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(obj);
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i915_gem_object_unpin_map(obj);
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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goto err_obj;
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rq->batch = vma;
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i915_request_get(rq);
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i915_vma_lock(vma);
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err = i915_request_await_object(rq, vma->obj, false);
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if (!err)
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err = i915_vma_move_to_active(vma, rq, 0);
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if (!err)
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err = rq->engine->emit_bb_start(rq,
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vma->node.start,
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PAGE_SIZE, 0);
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i915_vma_unlock(vma);
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i915_request_add(rq);
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if (err)
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goto err_rq;
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i915_gem_object_put(obj);
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intel_context_put(ce);
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rq->client_link.next = &(*prev)->client_link;
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*prev = rq;
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return 0;
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err_rq:
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i915_request_put(rq);
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err_obj:
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i915_gem_object_put(obj);
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err_ce:
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intel_context_put(ce);
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return err;
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}
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static int live_preempt_gang(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
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return 0;
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/*
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* Build as long a chain of preempters as we can, with each
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* request higher priority than the last. Once we are ready, we release
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* the last batch which then precolates down the chain, each releasing
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* the next oldest in turn. The intent is to simply push as hard as we
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* can with the number of preemptions, trying to exceed narrow HW
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* limits. At a minimum, we insist that we can sort all the user
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* high priority levels into execution order.
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*/
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for_each_engine(engine, gt, id) {
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struct i915_request *rq = NULL;
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struct igt_live_test t;
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IGT_TIMEOUT(end_time);
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int prio = 0;
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int err = 0;
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u32 *cs;
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if (!intel_engine_has_preemption(engine))
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continue;
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if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))
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return -EIO;
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do {
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struct i915_sched_attr attr = {
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.priority = I915_USER_PRIORITY(prio++),
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};
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err = create_gang(engine, &rq);
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if (err)
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break;
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/* Submit each spinner at increasing priority */
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engine->schedule(rq, &attr);
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if (prio <= I915_PRIORITY_MAX)
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continue;
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if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT))
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break;
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if (__igt_timeout(end_time, NULL))
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break;
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} while (1);
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pr_debug("%s: Preempt chain of %d requests\n",
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engine->name, prio);
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/*
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* Such that the last spinner is the highest priority and
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* should execute first. When that spinner completes,
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* it will terminate the next lowest spinner until there
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* are no more spinners and the gang is complete.
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*/
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cs = i915_gem_object_pin_map(rq->batch->obj, I915_MAP_WC);
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if (!IS_ERR(cs)) {
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*cs = 0;
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i915_gem_object_unpin_map(rq->batch->obj);
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} else {
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err = PTR_ERR(cs);
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intel_gt_set_wedged(gt);
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}
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while (rq) { /* wait for each rq from highest to lowest prio */
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struct i915_request *n =
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list_next_entry(rq, client_link);
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if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0) {
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struct drm_printer p =
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drm_info_printer(engine->i915->drm.dev);
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pr_err("Failed to flush chain of %d requests, at %d\n",
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prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT);
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intel_engine_dump(engine, &p,
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"%s\n", engine->name);
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err = -ETIME;
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}
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i915_request_put(rq);
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rq = n;
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}
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if (igt_live_test_end(&t))
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err = -EIO;
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if (err)
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return err;
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}
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return 0;
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}
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static int live_preempt_hang(void *arg)
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{
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struct intel_gt *gt = arg;
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@ -3028,6 +3223,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
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SUBTEST(live_suppress_self_preempt),
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SUBTEST(live_suppress_wait_preempt),
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SUBTEST(live_chain_preempt),
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SUBTEST(live_preempt_gang),
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SUBTEST(live_preempt_hang),
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SUBTEST(live_preempt_timeout),
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SUBTEST(live_preempt_smoke),
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