drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)
For gfx ring only. Compute is still todo. v2: add documentation v3: update to latest reset changes, integrate emit update patch. v4: fix count on wait_reg_mem for HDP flush v5: use old hdp flush method for fence v6: set valid bit for IB v7: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher
parent
841cf442fd
commit
2cae3bc3f3
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@ -1492,6 +1492,140 @@ static void cik_gpu_init(struct radeon_device *rdev)
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udelay(50);
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}
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/*
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* GPU scratch registers helpers function.
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*/
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/**
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* cik_scratch_init - setup driver info for CP scratch regs
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*
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* @rdev: radeon_device pointer
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*
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* Set up the number and offset of the CP scratch registers.
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* NOTE: use of CP scratch registers is a legacy inferface and
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* is not used by default on newer asics (r6xx+). On newer asics,
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* memory buffers are used for fences rather than scratch regs.
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*/
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static void cik_scratch_init(struct radeon_device *rdev)
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{
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int i;
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rdev->scratch.num_reg = 7;
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rdev->scratch.reg_base = SCRATCH_REG0;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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rdev->scratch.free[i] = true;
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rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
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}
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}
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/**
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* cik_fence_ring_emit - emit a fence on the gfx ring
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*
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* @rdev: radeon_device pointer
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* @fence: radeon fence object
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*
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* Emits a fence sequnce number on the gfx ring and flushes
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* GPU caches.
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*/
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void cik_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
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/* EVENT_WRITE_EOP - flush caches, send int */
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radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
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radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
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EOP_TC_ACTION_EN |
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EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
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EVENT_INDEX(5)));
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radeon_ring_write(ring, addr & 0xfffffffc);
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
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radeon_ring_write(ring, fence->seq);
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radeon_ring_write(ring, 0);
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/* HDP flush */
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/* We should be using the new WAIT_REG_MEM special op packet here
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* but it causes the CP to hang
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*/
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
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WRITE_DATA_DST_SEL(0)));
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radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
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radeon_ring_write(ring, 0);
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radeon_ring_write(ring, 0);
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}
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void cik_semaphore_ring_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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bool emit_wait)
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{
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uint64_t addr = semaphore->gpu_addr;
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unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
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radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
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radeon_ring_write(ring, addr & 0xffffffff);
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
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}
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/*
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* IB stuff
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*/
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/**
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* cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
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*
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* @rdev: radeon_device pointer
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* @ib: radeon indirect buffer object
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*
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* Emits an DE (drawing engine) or CE (constant engine) IB
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* on the gfx ring. IBs are usually generated by userspace
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* acceleration drivers and submitted to the kernel for
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* sheduling on the ring. This function schedules the IB
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* on the gfx ring for execution by the GPU.
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*/
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void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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u32 header, control = INDIRECT_BUFFER_VALID;
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if (ib->is_const_ib) {
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/* set switch buffer packet before const IB */
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radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
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radeon_ring_write(ring, 0);
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header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
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} else {
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u32 next_rptr;
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if (ring->rptr_save_reg) {
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next_rptr = ring->wptr + 3 + 4;
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radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
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radeon_ring_write(ring, ((ring->rptr_save_reg -
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PACKET3_SET_UCONFIG_REG_START) >> 2));
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radeon_ring_write(ring, next_rptr);
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} else if (rdev->wb.enabled) {
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next_rptr = ring->wptr + 5 + 4;
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radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
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radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
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radeon_ring_write(ring, next_rptr);
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}
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header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
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}
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control |= ib->length_dw |
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(ib->vm ? (ib->vm->id << 24) : 0);
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radeon_ring_write(ring, header);
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radeon_ring_write(ring,
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#ifdef __BIG_ENDIAN
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(2 << 0) |
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#endif
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(ib->gpu_addr & 0xFFFFFFFC));
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radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
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radeon_ring_write(ring, control);
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}
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/*
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* CP.
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* On CIK, gfx and compute now have independant command processors.
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@ -188,6 +188,21 @@
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#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
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#define GPU_HDP_FLUSH_REQ 0x54DC
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#define GPU_HDP_FLUSH_DONE 0x54E0
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#define CP0 (1 << 0)
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#define CP1 (1 << 1)
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#define CP2 (1 << 2)
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#define CP3 (1 << 3)
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#define CP4 (1 << 4)
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#define CP5 (1 << 5)
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#define CP6 (1 << 6)
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#define CP7 (1 << 7)
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#define CP8 (1 << 8)
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#define CP9 (1 << 9)
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#define SDMA0 (1 << 10)
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#define SDMA1 (1 << 11)
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#define GRBM_CNTL 0x8000
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#define GRBM_READ_TIMEOUT(x) ((x) << 0)
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@ -492,6 +507,49 @@
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# define RASTER_CONFIG_RB_MAP_2 2
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# define RASTER_CONFIG_RB_MAP_3 3
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#define VGT_EVENT_INITIATOR 0x28a90
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# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
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# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
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# define SAMPLE_STREAMOUTSTATS3 (3 << 0)
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# define CACHE_FLUSH_TS (4 << 0)
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# define CACHE_FLUSH (6 << 0)
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# define CS_PARTIAL_FLUSH (7 << 0)
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# define VGT_STREAMOUT_RESET (10 << 0)
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# define END_OF_PIPE_INCR_DE (11 << 0)
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# define END_OF_PIPE_IB_END (12 << 0)
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# define RST_PIX_CNT (13 << 0)
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# define VS_PARTIAL_FLUSH (15 << 0)
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# define PS_PARTIAL_FLUSH (16 << 0)
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# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
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# define ZPASS_DONE (21 << 0)
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# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
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# define PERFCOUNTER_START (23 << 0)
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# define PERFCOUNTER_STOP (24 << 0)
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# define PIPELINESTAT_START (25 << 0)
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# define PIPELINESTAT_STOP (26 << 0)
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# define PERFCOUNTER_SAMPLE (27 << 0)
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# define SAMPLE_PIPELINESTAT (30 << 0)
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# define SO_VGT_STREAMOUT_FLUSH (31 << 0)
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# define SAMPLE_STREAMOUTSTATS (32 << 0)
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# define RESET_VTX_CNT (33 << 0)
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# define VGT_FLUSH (36 << 0)
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# define BOTTOM_OF_PIPE_TS (40 << 0)
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# define DB_CACHE_FLUSH_AND_INV (42 << 0)
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# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
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# define FLUSH_AND_INV_DB_META (44 << 0)
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# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
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# define FLUSH_AND_INV_CB_META (46 << 0)
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# define CS_DONE (47 << 0)
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# define PS_DONE (48 << 0)
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# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
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# define THREAD_TRACE_START (51 << 0)
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# define THREAD_TRACE_STOP (52 << 0)
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# define THREAD_TRACE_FLUSH (54 << 0)
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# define THREAD_TRACE_FINISH (55 << 0)
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# define PIXEL_PIPE_STAT_CONTROL (56 << 0)
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# define PIXEL_PIPE_STAT_DUMP (57 << 0)
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# define PIXEL_PIPE_STAT_RESET (58 << 0)
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#define SCRATCH_REG0 0x30100
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#define SCRATCH_REG1 0x30104
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#define SCRATCH_REG2 0x30108
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@ -508,6 +566,8 @@
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#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
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#define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
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#define GRBM_GFX_INDEX 0x30800
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#define INSTANCE_INDEX(x) ((x) << 0)
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#define SH_INDEX(x) ((x) << 8)
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@ -597,11 +657,63 @@
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#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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#define PACKET3_DRAW_PREAMBLE 0x36
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#define PACKET3_WRITE_DATA 0x37
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#define WRITE_DATA_DST_SEL(x) ((x) << 8)
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/* 0 - register
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* 1 - memory (sync - via GRBM)
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* 2 - gl2
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* 3 - gds
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* 4 - reserved
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* 5 - memory (async - direct)
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*/
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#define WR_ONE_ADDR (1 << 16)
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#define WR_CONFIRM (1 << 20)
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#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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*/
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#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
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/* 0 - me
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* 1 - pfp
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* 2 - ce
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*/
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#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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#define PACKET3_MEM_SEMAPHORE 0x39
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# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
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# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
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# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
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# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
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# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
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#define PACKET3_COPY_DW 0x3B
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
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/* 0 - always
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* 1 - <
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* 2 - <=
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* 3 - ==
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* 4 - !=
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* 5 - >=
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* 6 - >
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*/
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#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
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/* 0 - reg
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* 1 - mem
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*/
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#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
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/* 0 - wait_reg_mem
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* 1 - wr_wait_wr_reg
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*/
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#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
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/* 0 - me
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* 1 - pfp
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*/
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#define PACKET3_INDIRECT_BUFFER 0x3F
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#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
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#define INDIRECT_BUFFER_VALID (1 << 23)
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#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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#define PACKET3_COPY_DATA 0x40
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#define PACKET3_PFP_SYNC_ME 0x42
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#define PACKET3_SURFACE_SYNC 0x43
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@ -646,12 +758,12 @@
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#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
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#define EOP_TCL1_ACTION_EN (1 << 16)
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#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
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#define CACHE_POLICY(x) ((x) << 25)
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#define EOP_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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#define TCL2_VOLATILE (1 << 27)
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#define EOP_TCL2_VOLATILE (1 << 27)
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#define DATA_SEL(x) ((x) << 29)
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/* 0 - discard
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* 1 - send low 32bit data
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@ -693,6 +805,8 @@
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#define PACKET3_SET_SH_REG_OFFSET 0x77
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#define PACKET3_SET_QUEUE_REG 0x78
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#define PACKET3_SET_UCONFIG_REG 0x79
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#define PACKET3_SET_UCONFIG_REG_START 0x00030000
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#define PACKET3_SET_UCONFIG_REG_END 0x00031000
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#define PACKET3_SCRATCH_RAM_WRITE 0x7D
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#define PACKET3_SCRATCH_RAM_READ 0x7E
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#define PACKET3_LOAD_CONST_RAM 0x80
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@ -702,6 +816,6 @@
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#define PACKET3_INCREMENT_DE_COUNTER 0x85
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#define PACKET3_WAIT_ON_CE_COUNTER 0x86
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#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
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#define PACKET3_SWITCH_BUFFER 0x8B
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#endif
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