MIPS: BCM63XX: add basic BCM6362 support
Add basic support for detecting and booting the BCM6362. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5009/ Acked-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jonas Gorski
Ralf Baechle
parent
13be798c57
commit
2c8aaf71b0
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@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
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bool "support 6358 CPU"
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select HW_HAS_PCI
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config BCM63XX_CPU_6362
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bool "support 6362 CPU"
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select HW_HAS_PCI
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config BCM63XX_CPU_6368
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bool "support 6368 CPU"
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select HW_HAS_PCI
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@ -726,11 +726,11 @@ void __init board_prom_init(void)
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u32 val;
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/* read base address of boot chip select (0)
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* 6328 does not have MPI but boots from a fixed address
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* 6328/6362 do not have MPI but boot from a fixed address
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*/
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if (BCMCPU_IS_6328())
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if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
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val = 0x18000000;
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else {
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} else {
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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}
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@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
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};
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static const unsigned long bcm6362_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6362)
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};
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static const int bcm6362_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6362)
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};
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static const unsigned long bcm6368_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6368)
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};
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@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(void)
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return (16 * 1000000 * n1 * n2) / m1;
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}
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case BCM6362_CPU_ID:
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{
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unsigned int tmp, mips_pll_fcvo;
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tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
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mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
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>> STRAPBUS_6362_FCVO_SHIFT;
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switch (mips_pll_fcvo) {
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case 0x03:
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case 0x0b:
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case 0x13:
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case 0x1b:
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return 240000000;
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case 0x04:
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case 0x0c:
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case 0x14:
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case 0x1c:
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return 160000000;
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case 0x05:
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case 0x0e:
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case 0x16:
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case 0x1e:
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case 0x1f:
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return 400000000;
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case 0x06:
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return 440000000;
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case 0x07:
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case 0x17:
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return 384000000;
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case 0x15:
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case 0x1d:
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return 200000000;
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default:
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return 320000000;
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}
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}
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case BCM6368_CPU_ID:
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{
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unsigned int tmp, p1, p2, ndiv, m1;
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@ -205,7 +250,7 @@ static unsigned int detect_memory_size(void)
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unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
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u32 val;
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if (BCMCPU_IS_6328())
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if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
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return bcm_ddr_readl(DDR_CSEND_REG) << 24;
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if (BCMCPU_IS_6345()) {
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@ -297,6 +342,10 @@ void __init bcm63xx_cpu_init(void)
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bcm63xx_regs_base = bcm6358_regs_base;
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bcm63xx_irqs = bcm6358_irqs;
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break;
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case BCM6362_CPU_ID:
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bcm63xx_regs_base = bcm6362_regs_base;
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bcm63xx_irqs = bcm6362_irqs;
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break;
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case BCM6368_CPU_ID:
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bcm63xx_regs_base = bcm6368_regs_base;
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bcm63xx_irqs = bcm6368_irqs;
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@ -82,6 +82,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
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#define ext_irq_cfg_reg2 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6362
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#define irq_stat_reg PERF_IRQSTAT_6362_REG
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#define irq_mask_reg PERF_IRQMASK_6362_REG
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#define irq_bits 64
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
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#define ext_irq_count 4
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6362
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#define ext_irq_cfg_reg2 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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#define irq_stat_reg PERF_IRQSTAT_6368_REG
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#define irq_mask_reg PERF_IRQMASK_6368_REG
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@ -170,6 +181,16 @@ static void bcm63xx_init_irq(void)
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ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
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break;
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case BCM6362_CPU_ID:
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irq_stat_addr += PERF_IRQSTAT_6362_REG;
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irq_mask_addr += PERF_IRQMASK_6362_REG;
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
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break;
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case BCM6368_CPU_ID:
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irq_stat_addr += PERF_IRQSTAT_6368_REG;
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irq_mask_addr += PERF_IRQMASK_6368_REG;
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@ -458,6 +479,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
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case BCM6338_CPU_ID:
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case BCM6345_CPU_ID:
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case BCM6358_CPU_ID:
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case BCM6362_CPU_ID:
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case BCM6368_CPU_ID:
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if (levelsense)
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reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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@ -36,6 +36,8 @@ void __init prom_init(void)
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mask = CKCTL_6348_ALL_SAFE_EN;
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else if (BCMCPU_IS_6358())
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mask = CKCTL_6358_ALL_SAFE_EN;
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else if (BCMCPU_IS_6362())
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mask = CKCTL_6362_ALL_SAFE_EN;
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else if (BCMCPU_IS_6368())
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mask = CKCTL_6368_ALL_SAFE_EN;
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else
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@ -85,6 +85,20 @@
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#define BCM6358_RESET_PCIE 0
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#define BCM6358_RESET_PCIE_EXT 0
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#define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK
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#define BCM6362_RESET_ENET 0
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#define BCM6362_RESET_USBH SOFTRESET_6362_USBH_MASK
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#define BCM6362_RESET_USBD SOFTRESET_6362_USBS_MASK
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#define BCM6362_RESET_DSL 0
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#define BCM6362_RESET_SAR SOFTRESET_6362_SAR_MASK
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#define BCM6362_RESET_EPHY SOFTRESET_6362_EPHY_MASK
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#define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK
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#define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK
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#define BCM6362_RESET_MPI 0
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#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \
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SOFTRESET_6362_PCIE_CORE_MASK)
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#define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
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#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
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#define BCM6368_RESET_ENET 0
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#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
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@ -119,6 +133,10 @@ static const u32 bcm6358_reset_bits[] = {
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__GEN_RESET_BITS_TABLE(6358)
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};
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static const u32 bcm6362_reset_bits[] = {
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__GEN_RESET_BITS_TABLE(6362)
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};
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static const u32 bcm6368_reset_bits[] = {
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__GEN_RESET_BITS_TABLE(6368)
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};
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@ -140,6 +158,9 @@ static int __init bcm63xx_reset_bits_init(void)
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} else if (BCMCPU_IS_6358()) {
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reset_reg = PERF_SOFTRESET_6358_REG;
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bcm63xx_reset_bits = bcm6358_reset_bits;
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} else if (BCMCPU_IS_6362()) {
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reset_reg = PERF_SOFTRESET_6362_REG;
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bcm63xx_reset_bits = bcm6362_reset_bits;
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} else if (BCMCPU_IS_6368()) {
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reset_reg = PERF_SOFTRESET_6368_REG;
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bcm63xx_reset_bits = bcm6368_reset_bits;
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@ -182,6 +203,13 @@ static const u32 bcm63xx_reset_bits[] = {
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#define reset_reg PERF_SOFTRESET_6358_REG
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6362
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static const u32 bcm63xx_reset_bits[] = {
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__GEN_RESET_BITS_TABLE(6362)
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};
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#define reset_reg PERF_SOFTRESET_6362_REG
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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static const u32 bcm63xx_reset_bits[] = {
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__GEN_RESET_BITS_TABLE(6368)
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@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
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case BCM6358_CPU_ID:
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perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
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break;
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case BCM6362_CPU_ID:
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perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
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break;
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}
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for (i = 0; i < 2; i++) {
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@ -14,6 +14,7 @@
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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#define BCM6358_CPU_ID 0x6358
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#define BCM6362_CPU_ID 0x6362
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#define BCM6368_CPU_ID 0x6368
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void __init bcm63xx_cpu_init(void);
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@ -86,6 +87,20 @@ unsigned int bcm63xx_get_cpu_freq(void);
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# define BCMCPU_IS_6358() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6362
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6362_CPU_ID
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# endif
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# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
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#else
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# define BCMCPU_IS_6362() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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@ -405,6 +420,62 @@ enum bcm63xx_regs_set {
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#define BCM_6358_MISC_BASE (0xdeadbeef)
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/*
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* 6362 register sets base address
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*/
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#define BCM_6362_DSL_LMEM_BASE (0xdeadbeef)
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#define BCM_6362_PERF_BASE (0xb0000000)
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#define BCM_6362_TIMER_BASE (0xb0000040)
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#define BCM_6362_WDT_BASE (0xb000005c)
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#define BCM_6362_UART0_BASE (0xb0000100)
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#define BCM_6362_UART1_BASE (0xb0000120)
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#define BCM_6362_GPIO_BASE (0xb0000080)
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#define BCM_6362_SPI_BASE (0xb0000800)
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#define BCM_6362_HSSPI_BASE (0xb0001000)
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#define BCM_6362_UDC0_BASE (0xdeadbeef)
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#define BCM_6362_USBDMA_BASE (0xb000c000)
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#define BCM_6362_OHCI0_BASE (0xb0002600)
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#define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6362_USBH_PRIV_BASE (0xb0002700)
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#define BCM_6362_USBD_BASE (0xb0002400)
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#define BCM_6362_MPI_BASE (0xdeadbeef)
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#define BCM_6362_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6362_PCIE_BASE (0xb0e40000)
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#define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6362_DSL_BASE (0xdeadbeef)
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#define BCM_6362_UBUS_BASE (0xdeadbeef)
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#define BCM_6362_ENET0_BASE (0xdeadbeef)
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#define BCM_6362_ENET1_BASE (0xdeadbeef)
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#define BCM_6362_ENETDMA_BASE (0xb000d800)
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#define BCM_6362_ENETDMAC_BASE (0xb000da00)
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#define BCM_6362_ENETDMAS_BASE (0xb000dc00)
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#define BCM_6362_ENETSW_BASE (0xb0e00000)
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#define BCM_6362_EHCI0_BASE (0xb0002500)
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#define BCM_6362_SDRAM_BASE (0xdeadbeef)
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#define BCM_6362_MEMC_BASE (0xdeadbeef)
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#define BCM_6362_DDR_BASE (0xb0003000)
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#define BCM_6362_M2M_BASE (0xdeadbeef)
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#define BCM_6362_ATM_BASE (0xdeadbeef)
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#define BCM_6362_XTM_BASE (0xb0007800)
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#define BCM_6362_XTMDMA_BASE (0xb000b800)
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#define BCM_6362_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_6362_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_6362_PCM_BASE (0xb000a800)
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#define BCM_6362_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6362_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6362_RNG_BASE (0xdeadbeef)
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#define BCM_6362_MISC_BASE (0xb0001800)
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#define BCM_6362_NAND_REG_BASE (0xb0000200)
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#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
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#define BCM_6362_LED_BASE (0xb0001900)
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#define BCM_6362_IPSEC_BASE (0xb0002800)
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#define BCM_6362_IPSEC_DMA_BASE (0xb000d000)
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#define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000)
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#define BCM_6362_WLAN_D11_BASE (0xb0005000)
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#define BCM_6362_WLAN_SHIM_BASE (0xb0007000)
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/*
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* 6368 register sets base address
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*/
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@ -564,6 +635,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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#ifdef CONFIG_BCM63XX_CPU_6358
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__GEN_RSET(6358)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6362
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__GEN_RSET(6362)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6368
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__GEN_RSET(6368)
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#endif
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@ -819,6 +893,71 @@ enum bcm63xx_irq {
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#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
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#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
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/*
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* 6362 irqs
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*/
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#define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
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#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3)
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#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28)
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#define BCM_6362_UDC0_IRQ 0
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#define BCM_6362_ENET0_IRQ 0
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#define BCM_6362_ENET1_IRQ 0
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#define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14)
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#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5)
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#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
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#define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20)
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#define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21)
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#define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22)
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#define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23)
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#define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24)
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#define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25)
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#define BCM_6362_PCMCIA_IRQ 0
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#define BCM_6362_ENET0_RXDMA_IRQ 0
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#define BCM_6362_ENET0_TXDMA_IRQ 0
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#define BCM_6362_ENET1_RXDMA_IRQ 0
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#define BCM_6362_ENET1_TXDMA_IRQ 0
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#define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30)
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#define BCM_6362_ATM_IRQ 0
|
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#define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0)
|
||||
#define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1)
|
||||
#define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2)
|
||||
#define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3)
|
||||
#define BCM_6362_ENETSW_TXDMA0_IRQ 0
|
||||
#define BCM_6362_ENETSW_TXDMA1_IRQ 0
|
||||
#define BCM_6362_ENETSW_TXDMA2_IRQ 0
|
||||
#define BCM_6362_ENETSW_TXDMA3_IRQ 0
|
||||
#define BCM_6362_XTM_IRQ 0
|
||||
#define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12)
|
||||
|
||||
#define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1)
|
||||
#define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6)
|
||||
#define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
|
||||
#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
|
||||
#define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12)
|
||||
#define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
|
||||
#define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15)
|
||||
#define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
|
||||
#define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
|
||||
#define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
|
||||
#define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
|
||||
#define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
|
||||
#define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27)
|
||||
#define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29)
|
||||
#define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4)
|
||||
#define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5)
|
||||
#define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6)
|
||||
#define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7)
|
||||
#define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8)
|
||||
#define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9)
|
||||
#define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10)
|
||||
#define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11)
|
||||
|
||||
/*
|
||||
* 6368 irqs
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
|
|||
return 8;
|
||||
case BCM6345_CPU_ID:
|
||||
return 16;
|
||||
case BCM6362_CPU_ID:
|
||||
return 48;
|
||||
case BCM6368_CPU_ID:
|
||||
return 38;
|
||||
case BCM6348_CPU_ID:
|
||||
|
|
|
|||
|
|
@ -112,6 +112,39 @@
|
|||
CKCTL_6358_USBSU_EN | \
|
||||
CKCTL_6358_EPHY_EN)
|
||||
|
||||
#define CKCTL_6362_ADSL_QPROC_EN (1 << 1)
|
||||
#define CKCTL_6362_ADSL_AFE_EN (1 << 2)
|
||||
#define CKCTL_6362_ADSL_EN (1 << 3)
|
||||
#define CKCTL_6362_MIPS_EN (1 << 4)
|
||||
#define CKCTL_6362_WLAN_OCP_EN (1 << 5)
|
||||
#define CKCTL_6362_SWPKT_USB_EN (1 << 7)
|
||||
#define CKCTL_6362_SWPKT_SAR_EN (1 << 8)
|
||||
#define CKCTL_6362_SAR_EN (1 << 9)
|
||||
#define CKCTL_6362_ROBOSW_EN (1 << 10)
|
||||
#define CKCTL_6362_PCM_EN (1 << 11)
|
||||
#define CKCTL_6362_USBD_EN (1 << 12)
|
||||
#define CKCTL_6362_USBH_EN (1 << 13)
|
||||
#define CKCTL_6362_IPSEC_EN (1 << 14)
|
||||
#define CKCTL_6362_SPI_EN (1 << 15)
|
||||
#define CKCTL_6362_HSSPI_EN (1 << 16)
|
||||
#define CKCTL_6362_PCIE_EN (1 << 17)
|
||||
#define CKCTL_6362_FAP_EN (1 << 18)
|
||||
#define CKCTL_6362_PHYMIPS_EN (1 << 19)
|
||||
#define CKCTL_6362_NAND_EN (1 << 20)
|
||||
|
||||
#define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \
|
||||
CKCTL_6362_ADSL_QPROC_EN | \
|
||||
CKCTL_6362_ADSL_AFE_EN | \
|
||||
CKCTL_6362_ADSL_EN | \
|
||||
CKCTL_6362_SAR_EN | \
|
||||
CKCTL_6362_PCM_EN | \
|
||||
CKCTL_6362_IPSEC_EN | \
|
||||
CKCTL_6362_USBD_EN | \
|
||||
CKCTL_6362_USBH_EN | \
|
||||
CKCTL_6362_ROBOSW_EN | \
|
||||
CKCTL_6362_PCIE_EN)
|
||||
|
||||
|
||||
#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
|
||||
#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
|
||||
#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
|
||||
|
|
@ -153,6 +186,7 @@
|
|||
#define PERF_IRQMASK_6345_REG 0xc
|
||||
#define PERF_IRQMASK_6348_REG 0xc
|
||||
#define PERF_IRQMASK_6358_REG 0xc
|
||||
#define PERF_IRQMASK_6362_REG 0x20
|
||||
#define PERF_IRQMASK_6368_REG 0x20
|
||||
|
||||
/* Interrupt Status register */
|
||||
|
|
@ -161,6 +195,7 @@
|
|||
#define PERF_IRQSTAT_6345_REG 0x10
|
||||
#define PERF_IRQSTAT_6348_REG 0x10
|
||||
#define PERF_IRQSTAT_6358_REG 0x10
|
||||
#define PERF_IRQSTAT_6362_REG 0x28
|
||||
#define PERF_IRQSTAT_6368_REG 0x28
|
||||
|
||||
/* External Interrupt Configuration register */
|
||||
|
|
@ -169,6 +204,7 @@
|
|||
#define PERF_EXTIRQ_CFG_REG_6345 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6348 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6358 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6362 0x18
|
||||
#define PERF_EXTIRQ_CFG_REG_6368 0x18
|
||||
|
||||
#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
|
||||
|
|
@ -197,6 +233,7 @@
|
|||
#define PERF_SOFTRESET_REG 0x28
|
||||
#define PERF_SOFTRESET_6328_REG 0x10
|
||||
#define PERF_SOFTRESET_6358_REG 0x34
|
||||
#define PERF_SOFTRESET_6362_REG 0x10
|
||||
#define PERF_SOFTRESET_6368_REG 0x10
|
||||
|
||||
#define SOFTRESET_6328_SPI_MASK (1 << 0)
|
||||
|
|
@ -259,6 +296,22 @@
|
|||
#define SOFTRESET_6358_PCM_MASK (1 << 13)
|
||||
#define SOFTRESET_6358_ADSL_MASK (1 << 14)
|
||||
|
||||
#define SOFTRESET_6362_SPI_MASK (1 << 0)
|
||||
#define SOFTRESET_6362_IPSEC_MASK (1 << 1)
|
||||
#define SOFTRESET_6362_EPHY_MASK (1 << 2)
|
||||
#define SOFTRESET_6362_SAR_MASK (1 << 3)
|
||||
#define SOFTRESET_6362_ENETSW_MASK (1 << 4)
|
||||
#define SOFTRESET_6362_USBS_MASK (1 << 5)
|
||||
#define SOFTRESET_6362_USBH_MASK (1 << 6)
|
||||
#define SOFTRESET_6362_PCM_MASK (1 << 7)
|
||||
#define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8)
|
||||
#define SOFTRESET_6362_PCIE_MASK (1 << 9)
|
||||
#define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10)
|
||||
#define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11)
|
||||
#define SOFTRESET_6362_DDR_PHY_MASK (1 << 12)
|
||||
#define SOFTRESET_6362_FAP_MASK (1 << 13)
|
||||
#define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14)
|
||||
|
||||
#define SOFTRESET_6368_SPI_MASK (1 << 0)
|
||||
#define SOFTRESET_6368_MPI_MASK (1 << 3)
|
||||
#define SOFTRESET_6368_EPHY_MASK (1 << 6)
|
||||
|
|
@ -1240,7 +1293,7 @@
|
|||
#define SPI_6348_RX_DATA 0x80
|
||||
#define SPI_6348_RX_DATA_SIZE 0x3f
|
||||
|
||||
/* BCM 6358/6368 SPI core */
|
||||
/* BCM 6358/6262/6368 SPI core */
|
||||
#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
|
||||
#define SPI_6358_MSG_CTL_WIDTH 16
|
||||
#define SPI_6358_MSG_DATA 0x02
|
||||
|
|
@ -1316,6 +1369,12 @@
|
|||
#define SERDES_PCIE_EN (1 << 0)
|
||||
#define SERDES_PCIE_EXD_EN (1 << 15)
|
||||
|
||||
#define MISC_STRAPBUS_6362_REG 0x14
|
||||
#define STRAPBUS_6362_FCVO_SHIFT 1
|
||||
#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
|
||||
#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
|
||||
#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
|
||||
|
||||
#define MISC_STRAPBUS_6328_REG 0x240
|
||||
#define STRAPBUS_6328_FCVO_SHIFT 7
|
||||
#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
|
|||
return 1;
|
||||
break;
|
||||
case BCM6328_CPU_ID:
|
||||
case BCM6362_CPU_ID:
|
||||
case BCM6368_CPU_ID:
|
||||
if (offset >= 0xb0000000 && offset < 0xb1000000)
|
||||
return 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue