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ARM: tlb: don't perform inner-shareable invalidation for local BP ops 

Now that the ASID allocator doesn't require inner-shareable maintenance,
we can convert the local_bp_flush_all function to perform only
non-shareable flushing, in a similar manner to the TLB invalidation
routines.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon 2013-02-18 22:07:47 +00:00
parent 587b9b6487
commit 2c813980c6
2 changed files with 21 additions and 3 deletions
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22
arch/arm/include/asm/tlbflush.h
View File

@ -531,15 +531,33 @@ static inline void __flush_tlb_kernel_page(unsigned long kaddr)
* Branch predictor maintenance is paired with full TLB invalidation, so
* there is no need for any barriers here.
*/
static inline void __local_flush_bp_all(void)
{
const int zero = 0;
const unsigned int __tlb_flag = __cpu_tlb_flags;
if (tlb_flag(TLB_V6_BP))
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
}
static inline void local_flush_bp_all(void)
{
const int zero = 0;
const unsigned int __tlb_flag = __cpu_tlb_flags;
__local_flush_bp_all();
if (tlb_flag(TLB_V7_UIS_BP))
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
}
static inline void __flush_bp_all(void)
{
const int zero = 0;
const unsigned int __tlb_flag = __cpu_tlb_flags;
__local_flush_bp_all();
if (tlb_flag(TLB_V7_UIS_BP))
asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero));
else if (tlb_flag(TLB_V6_BP))
asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero));
}
#include <asm/cputype.h>

2
arch/arm/kernel/smp_tlb.c
View File

@ -173,5 +173,5 @@ void flush_bp_all(void)
if (tlb_ops_need_broadcast())
on_each_cpu(ipi_flush_bp_all, NULL, 1);
else
local_flush_bp_all();
__flush_bp_all();
}